Micronas SDA 6000, User Manual

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SDA 6000
PRELIMINARY DATA SHEET
Version 2.1
Interrupt and Trap Functions
5 - 4 Micronas
5.1 Interrupt System Structure
M2 provides up to 33 separate interrupt nodes that may be assigned to 16 priority levels.
Each node is associated with an interrupt input line in the Interrupt System Interface of
the CPU. In order to support modular and consistent software design techniques, all
interrupt nodes are supplied with a separate interrupt control register and interrupt
vector. The control register contains the interrupt request flag, the interrupt enable bit,
and the interrupt priority of the associated node.
The C166 architecture provides a vectored interrupt system. In this system specific
vector locations in the memory space are reserved for the reset, trap, and interrupt
service functions. Whenever a request occurs, the CPU branches to the location that is
associated with the respective interrupt source. This allows direct identification of the
source that caused the request. The only exceptions are the class B hardware traps,
which all share the same interrupt vector. The status flags in the Trap Flag Register
(TFR) can then be used to determine which exception caused the trap. For the special
software TRAP instruction, the vector address is specified by the operand field of the
instruction, which is a seven bit trap number.
The reserved vector locations build a jump table in the low end of the address space
(segment 0). The jump table is made up of the appropriate jump instructions that transfer
control to the interrupt or trap service routines, which may be located anywhere within
the address space. The entries of the jump table are located at the lowest addresses in
code segment 0 of the address space. Each entry occupies 2 words, except for the reset
vector and the hardware trap vectors which occupy 4 or 8 words.
5.1.1 Interrupt Allocation Table
M2 provides 33 separate interrupt nodes that may be assigned to 16 priority levels. In
addition to the standard peripheral and external interrupts, there are some teletext
related interrupts which support the realtime processing of the sliced data and the
generation of the graphical data. Its fast external interrupt inputs are sampled every 3 ns
and are even able to recognize very short external signals.
The Table 5-1 lists all sources that are capable of requesting interrupt or PEC service in
M2, the associated interrupt vectors, their locations and the associated trap numbers. It
also lists the mnemonics of the affected interrupt request flags and their corresponding
interrupt enable flags. The mnemonics are composed of a part that specifies the
respective source, followed by a part that specifies their function (IR = Interrupt Request
flag, IE = Interrupt Enable flag).