Micronas SDA 6000, User Manual

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SDA 6000
PRELIMINARY DATA SHEET
Version 2.1
Peripherals
7 - 55 Micronas
7.3.1.3 Asynchronous Reception
Asynchronous reception is initiated by a falling edge (1-to-0 transition) on pin RXD0,
provided that bits S0R and S0REN are set. The receive data input pin RXD0 is sampled
at 16 times the rate of the selected baud rate. A majority decision of the 7th, 8th and 9th
sample determines the effective bit value. This avoids erroneous results that may be
caused by noise.
If the detected value is not equal to ‘0’ when the start bit is sampled, the receive circuit
is reset and waits for the next 1-to-0 transition at pin RXD0. If the start bit proves valid,
the receive circuit continues sampling and shifts the incoming data frame into the receive
shift register.
When the last stop bit has been received, the content of the receive shift register is
transferred to the receive data buffer register S0RBUF. Simultaneously, the receive
interrupt request line S0RIR is activated after the 9th sample in the last stop bit time slot
(as programmed), regardless whether valid stop bits have been received or not. The
receive circuit then waits for the next start bit (1-to-0 transition) at the receive data input
pin.
The receiver input pin RXD0 must be configured for input.
Asynchronous reception is stopped by clearing bit S0REN. A currently received frame is
completed including the generation of the receive interrupt request and an error interrupt
request, if appropriate. Start bits that follow this frame will not be recognized.
Note: In wake-up mode received frames are only transferred to the receive buffer
register, if the 9th bit (the wake-up bit) is equal to ‘1’. If this bit is equal to ‘0’, no
receive interrupt request will be activated and no data transferred.
IrDA Mode
The duration of the IrDA pulse is normally 3/16 of a bit period. The IrDA standard also
allows the pulse duration to be independent of the baud rate or bit period. In this case
the transmitted pulse always has the width corresponding to the 3/16 pulse width at
115.2 KBaud which is 1.67
←
s. Both bit period dependent or fixed IrDA pulse width
generation can be selected. The IrDA pulse width mode is selected by bit S0IRPW,
which is located in register S0PWM.
In case of a fixed IrDA pulse width generation, the lower 8 bits in register S0PWM are
used to adapt the IrDA pulse width to a fixed value of e.g. 1.67
←
s. The fixed IrDA pulse
width is generated by a programmable timer as shown in Figure 7-28 .