Micronas SDA 6000, User Manual

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SDA 6000
PRELIMINARY DATA SHEET
Version 2.1
Peripherals
7 - 24 Micronas
T3EUD or both inputs T3IN and T3EUD. The active edge is controlled by bit field CI in
register T5CON.
The maximum input frequency for the capture trigger signal at CAPIN is
f
hw_clk
/2
(BPS2 = ‘01’). To ensure that a transition of the capture trigger signal is correctly
recognized, its level should be held for at least 2
f
hw_clk
cycles (BPS2 = ‘01’) before it
changes.
When the timer T3 capture trigger is enabled (CT3 is set), register CAPREL captures the
contents of T5 when transitions of the selected input(s) occur. These values can be used
to measure T3’s input signals. This is useful e.g. when T3 operates in incremental
interface mode, in order to derive dynamic information (speed acceleration) from the
input signals.
When a selected transition at the external input line CAPIN is detected, the contents of
the auxiliary timer T5 are latched into register CAPREL, and interrupt request flag CRIR
is set. At the same time, timer T5 can be cleared to 0000
H
. This option is controlled by
bit T5CLR in register T5CON. If T5CLR = ‘0’, the contents of timer T5 are not affected
by a capture. If T5CLR = ‘1’, timer T5 is cleared after the current timer value has been
latched into register CAPREL.
Note: Bit T5SC only controls whether a capture is performed or not. If T5SC = ‘0’, the
input line CAPIN can still be used to clear timer T5 or as an external interrupt input.
This interrupt is controlled by the CAPREL interrupt control register CRIC.
Figure 7-17 Timer Block 2 Register CAPREL in Capture Mode
UEB11208
Auxiliary Timer T5
Up/Down
Interrupt
Request
Interrupt
Request
T5CLR
T5SC
T5CC
Edge
Select
CI
MUX
CAPREL Register
CAPIN
T3IN/
T3EUD
Input
Clock
CT3