Micronas SDA 6000, User Manual

Page: 245 / 412

SDA 6000
PRELIMINARY DATA SHEET
Version 2.1
Peripherals
7 - 87 Micronas
Figure 7-40 Serial Clock Phase and Polarity Options
7.4.1 Full-Duplex Operation
The different devices are connected by three lines. The definition of these lines is always
determined by the master: the line connected to the master’s data output pin MTSR is
the transmit line, the receive line is connected to its data input line MRST, and the clock
line is connected to pin SCLK. Only the device selected for master operation generates
and outputs the serial clock on pin SCLK. All slaves receive this clock, so their pin SCLK
must be switched to input mode. The output of the master’s shift register is connected to
the external transmit line, which in turn is connected to the slaves’ shift register input.
The output of the slaves’ shift register is connected to the external receive line in order
to enable the master to receive the data shifted out of the slave. The external
connections are hard-wired, the function and direction of these pins is determined by the
master or slave operation of the individual device.
Note: The shift direction shown in the diagram applies to MSB-first operation as well as
to LSB-first operation.
When initializing the devices in this configuration, one device must be selected for
master operation while all other devices must be programmed for slave operation.
Initialization includes the operating mode of the device’s SSC and also the function of
the respective port lines.
UED11159
SSC0
PO
SSC0
PH
0 0
0 1
1 0
1 1
Pins
MTSR0/MRST0
Transmit Data
Shift Clock
SCLK
Shift Data
First Bit
Latch Data
Last Bit