Micronas SDA 6000, User Manual

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1 - 7 Micronas
Type Package
SDA 6000 P-MQFP-128-2
Teletext Decoder with Embedded 16-bit Controller
M2
Version 2.1 CMOS
P-MQFP-128-2
SDA 6000
PRELIMINARY DATA SHEET
Version 2.1
Overview
1.1 Features
General
• Level 1.5, 2.5, 3.5 WST Display Compatible
• Fast External Bus Interface for SDRAM (Up to
8 MByte) and ROM or Flash-ROM (Up to 4 MByte)
• Embedded General Purpose 16 Bit CPU (Also used
as TV-System Controller, C16x Compatible)
• Display Generation Based on Pixel Memory
• Program Code also Executable From External
SDRAM
• Embedded Refresh Controller for External SDRAM
• Enhanced Programmable Low Power Modes
• Single 6 MHz Crystal Oscillator
• Multinorm H/V-Display Synchronization in Master or Slave Mode
• Free Programmable Pixel Clock from 10 MHz to 50 MHz
• Pixel Clock Independent from CPU Clock
• 3
⌠
6 Bits RGB-DACs On-Chip
• Supply Voltage 2.5 and 3.3 V
• P-MQFP-128 Package
Microcontroller Features
• 16-bit C166-CPU Kernel (C16x Compatible)
• 60 ns Instruction Cycle Time
• 2 KBytes Dual Ported IRAM
• 2 KBytes XRAM On-chip
• General Purpose Timer Units (GPT1 and GPT2).
• Asynchronous/Synchronous Serial Interface (ASC0) with IrDA Support. Full-duplex
Asynchronous Up To 2 MBaud or Half-duplex Synchronous up to 4.1 MBaud.