Micronas SDA 6000, User Manual

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SDA 6000
PRELIMINARY DATA SHEET
Version 2.1
Peripherals
7 - 27 Micronas
bit T6OTL will be toggled. This signal has 8 times more transitions than the signal which
is applied to line CAPIN.
A certain deviation of the output frequency is generated by the fact that timer T5 will
count actual time units (e.g. T5 running at 1 MHz will capture the value 64
H
/100
D
for a
10 KHz input signal) while T6OTL will only toggle on an underflow of T6 (i.e. the
transition from 0000
H
to FFFF
H
). In the above mentioned example, T6 would count down
from 64
H
so the underflow would occur after 101 T6 timing ticks. The actual output
frequency then is 79.2 KHz instead of the expected 80 KHz.
This can be solved by activating the capture correction (T5CC = ‘1’). If the capture
correction is actived the content of T5 is decremented by 1 before being captured. The
deviation described is eliminated (in the example T5 would capture 63
H
/99
D
and the
output frequency would be 80 KHz).
The underflow signal of timer T6 can furthermore be used to clock one or more of the
CAPCOM unit’s timers, which gives the user the possibility to set compare operations
based on a finer resolution than that of the external operations. This connection is
accomplished through the T6OFL signal.
7.1.3 GPT Registers
All available kernel registers are summarized in Table 7-8 .
Function Control Registers
The operating mode of the core timer T3 is configured and controlled by its bit-
addressable control register T3CON.
Table 7-8 GPT Register Summary
Name Reset Value Description
T2CON 0000
H
Timer 2 Control Register
T3CON 0000
H
Timer 3 Control Register
T4CON 0000
H
Timer 4 Control Register
T5CON 0000
H
Timer 5 Control Register
T6CON 0000
H
Timer 6 Control Register
CAPREL 0000
H
Capture/Reload Register
T2 0000
H
Timer 2 Register
T3 0000
H
Timer 3 Register
T4 0000
H
Timer 4 Register
T5 0000
H
Timer 5 Register
T6 0000
H
Timer 6 Register