Micronas SDA 6000, User Manual

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SDA 6000
PRELIMINARY DATA SHEET
Version 2.1
C16X Microcontroller
4 - 34 Micronas
possible conflicts (e.g. multiple usage of buses) in a time optimized way and thus usually
avoids the pipeline being noticed by the user. However, there are some very rare cases,
where the CPU, being a pipelined machine, requires attention by the programmer. In
these cases the delays caused by pipeline conflicts can be used for other instructions in
order to optimize performance.
Context Pointer Updating
An instruction which calculates a physical GPR operand address via the CP register, is
mostly not capable of using a new CP value, which is to be updated by an immediately
preceding instruction. Thus, to make sure that the new CP value is used, at least one
instruction must be inserted between a CP-changing and a subsequent GPR-using
instruction, as shown in the following example:
I
n
: SCXT CP, #0FC00h ; select a new context
I
n+1
:
…
. ; must not be an instruction using a GPR
I
n+2
: MOV R0, #dataX ; write to GPR 0 in the new context
Data Page Pointer Updating
An instruction, which calculates a physical operand address via a particular DPPn (n = 0
to 3) register, is mostly not capable of using a new DPPn register value, which is to be
updated by an immediately preceding instruction. Thus, to make sure that the new DPPn
register value is used, at least one instruction must be inserted between a DPPn-
changing instruction and a subsequent instruction which implicitly uses DPPn via a long
or indirect addressing mode, as shown in the following example:
I
n
: MOV DPP0, #4 ; select data page 4 via DPP0
I
n+1
:
…
. ; must not be an instruction using DPP0
I
n+2
: MOV DPP0:0000H, R1; move contents of R1 to address location
01’0000
H
; (in data page 4) supposed segmentation
is enabled
Explicit Stack Pointer Updating
None of the RET, RETI, RETS, RETP or POP instructions are capable of correctly using
a new SP register value, which is to be updated by an immediately preceding instruction.
Thus, in order to use the new SP register value without erroneously performed stack
accesses, at least one instruction must be inserted between an explicitly SP-writing and
any subsequent just mentioned implicitly SP-using instructions, as shown in the following
example:
I
n
: MOV SP, #0FA40H; select a new top of stack
I
n+1
:
…
. ; must not be an instruction popping
operands
; from the system stack