Micronas SDA 6000, User Manual

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SDA 6000
PRELIMINARY DATA SHEET
Version 2.1
Peripherals
7 - 80 Micronas
The fractional divider register FDV contains the 9-bit divider value for the fractional
divider (asynchronous mode only). It is also used for reference clock generation of the
autobaud detection unit.
The IrDA pulse mode and width register PMW contains the 8-bit IrDA pulse width value
and the IrDA pulse width mode select bit. This register is only required in the IrDA
operating mode.
S0BG
Baud Rate Timer/Reload Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 BR_VALUE
Field Bits Type Value Description
BR_VALUE 12-0 rw all Baud Rate Timer/Reload Register Value
Reading BG returns the 13-bit content of
the baud rate timer (bits 15 … 13 return 0);
writing BG loads the baud rate timer reload
register (bits 15 … 13 are don’t care). BG
should only be written if CON_R = ‘0’.
S0FDV
Fractional Divider Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 FD_VALUE
Field Bits Type Value Description
FD_VALUE 8-0 rw all Fractional Divider Register Value
FDV contains the 9-bit value n of the
fractional divider which defines the
fractional divider ratio:
n/512 n = 0-511). With n = 0, the fractional
divider is switched off (input = output
frequency,
f
DIV
=
f
MOD
).