Micronas SDA 6000, User Manual

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SDA 6000
PRELIMINARY DATA SHEET
Version 2.1
Peripherals
7 - 86 Micronas
transferred, the contents of the shift register are moved to the Receive Buffer SSCRB
and a receive interrupt request line (SSCRIR) will be activated. If no further transfer is to
take place (SSCTB is empty), SSC0BSY will be cleared at the same time. Software
should not modify SSC0BSY, as this flag is hardware controlled.
Note: Only one SSC (etc.) can be master at a given time.
The transfer of serial data bits can be programmed in many respects:
• The data width can be chosen from 2 bits to 16 bits
• A transfer may start with the LSB or the MSB
• The shift clock may be idle low or idle high
• The data bits may be shifted with the leading or trailing edge of the clock signal
• The baud rate may be set from 254 Baud up to 16.66 MBaud (@ 33.33 MHz module
clock)
• The shift clock can be generated (master) or received (slave)
These features allow the adaptation of the SSC0 to a wide range of applications, where
serial data transfer is required.
The Data Width Selection supports the transfer of frames of any data length, from 2-bit
‘characters’ up to 16-bit ‘characters’. Starting with the LSB (SSC0HB = ‘0’) allows
communication e.g. with an SSC device in synchronous mode (C166 family) or 8051 like
serial interfaces. Starting with the MSB (SSC0HB = ‘1’) allows operation compatible with
the SPI interface.
Regardless which data width is selected and whether the MSB or the LSB is transmitted
first, the transfer data is always right aligned in registers SSCTB and SSCRB, with the
LSB of the transfer data in bit 0 of these registers. The data bits are rearranged for
transfer by the internal shift register logic. The unselected bits of SSCTB are ignored, the
unselected bits of SSCRB will not be valid and should be ignored by the receiver service
routine.
The Clock Control allows the transmit and receive behavior of the SSC0 to be adapted
to a variety of serial interfaces. A specific clock edge (rising or falling) is used to shift out
transmit data, while the other clock edge is used to latch in receive data. Bit SSC0PH
selects the leading edge or the trailing edge for each function. Bit SSC0PO selects the
level of the clock line in the idle state. So for an idle-high clock the leading edge is a
falling one, a 1-to-0 transition (see
Figure 7-40 ).