Micronas SDA 6000, User Manual

Page: 95 / 412

SDA 6000
PRELIMINARY DATA SHEET
Version 2.1
Interrupt and Trap Functions
5 - 9 Micronas
xxIC Reset Value: - - 00
H
The Interrupt Request Flag is set by hardware whenever a service request from the
respective source occurs. It is cleared automatically upon entry into the interrupt service
routine or upon a PEC service. In the case of PEC service, the Interrupt Request flag
remains set if the COUNT field in register PECCx of the selected PEC channel
decrements to zero. This allows a normal CPU interrupt to respond to a completed PEC
block transfer.
Note: Modifying the Interrupt Request flag via software causes the same effect as if it
had been set or cleared by hardware.
Interrupt Priority Level and Group Level
The four bits of an ILVL bit field specify the priority level of a service request for the
arbitration of simultaneous requests. The priority increases with the numerical value of
ILVL, so 0000
B
is the lowest and 1111
B
is the highest priority level.
When more than one interrupt request on a specific level becomes active at the same
time, the values in the respective GLVL bit fields are used for second level arbitration to
select one request for servicing. Again the group priority increases with the numerical
value of GLVL, so 00
B
is the lowest and 11
B
is the highest group priority.
Bit Function
GLVL Group Level
Defines the internal order for simultaneous requests of the same priority.
3: Highest
group priority
0: Lowest group priority
ILVL Interrupt Priority Level
Defines the priority level for the arbitration of requests.
F
H
: Highest priority level
0
H
: Lowest priority level
xxIE Interrupt Enable Control Bit (individually enables/disables a specific
source)
‘0’:
Interrupt request is disabled
‘1’: Interrupt Request is enabled
xxIR Interrupt Request Flag
‘0’: No request pending
‘1’: This source has raised an interrupt request
5 4 3 2 1 0 11 10 9 8 7 6 15 14 13 12
rw rw - - - - rw rw - - - -
xxIE xxIR GLVL ILVL