Micronas SDA 6000, User Manual

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SDA 6000
PRELIMINARY DATA SHEET
Version 2.1
Peripherals
7 - 7 Micronas
In addition, T3OTL can be used in conjunction with the timer over/underflows as an input
for the counter function or as a trigger source for the reload function of the auxiliary
timers T2 and T4. For this purpose, the state of T3OTL does not have to be available at
any port pin, because an internal connection is provided for this option.
Timer 3 in Timer Mode
Timer mode for the core timer T3 is selected by setting bit field T3M in register T3CON
to ‘000
B
’.
In this mode, T3 is clocked with the system clock
f
hw_clk
divided by a programmable
prescaler, which is controlled by bit field T3I and BPS1. The input frequency
f
T3
for timer
T3 and its resolution
r
T3
are scaled linearly with lower module clock frequencies, as can
be seen from the following formula:
Table 7-2 gives an overview for timer resolutions depending on prescaler factors.
This formula also applies to the Gated Timer Mode of T3 and to the auxiliary timers T2
and T4 in timer and gated timer mode.
Table 7-2
f
MOD
=
33.33 MHz
Timer Input Selection T2I / T3I / T4I
000
B
000
B
001
B
010
B
011
B
100
B
101
B
110
B
111
B
FM = 1 0 0 0 0 0 0 0 0
Prescaler factor 4 8 16 32 64 128 256 512 1024
Input Frequency 2.08
MHz 4.16
MHz 2.08
MHz 1.04
MHz 521.83
kHz 260.41
kHz 130.20
kHz 65.10
kHz 32.55
kHz
Resolution 120
ns 240
ns 480
ns 960
ns 1.92
←
s
3.84
←
s
7.68
←
s
15.36
←
s
30.72
←
s
Period 7.86
ms 15.72
ms 31.45
ms 62.91
ms 125.82
ms 251.6
ms 503
ms 1
s 2.01
s
f
T3
=
f
hw_clk
BPS1
⌠
2
<T3I>
r
T3
[ms] =
f
hw_clk
[MHz]
BPS1
⌠
2
<T3I>