Micronas SDA 6000, User Manual

Page: 286 / 412

SDA 6000
PRELIMINARY DATA SHEET
Version 2.1
Clock System
8 - 5 Micronas
One, the 33 MHz system clock (
f
CPU
) supplies the processor, all processor related
peripherals, the sync timing logic, the A/D converters and the slicer.
The second clock system (100/66 MHZ) (
f
EBI
) is used to clock the external bus interface,
the display generator, the CLUTs and the input part of the display FIFO. This clock starts
at 66 MHz after hardware reset. It can be configured to 100 MHz during the initialization
sequence.
The frequency of the latter clock system can be changed via bit CLKCON in register
SYSCON2. The refresh rate of the external SDRAM is always kept constant,
independent of the selected system clock frequency.
The third clock system runs the pixel clock ( f
PIX
), which is programmable in a range of
10 … 50 MHz. It serves the output part of the display FIFO and the D/A converters. The
pixel clock is derived from the high frequency output of the PLL and it is phase shifted
line by line to the positive edge of the horizontal sync signal (normal polarity). Because
the final display clock is derived from a DTO (digital time oscillator) it has no equidistant
clock periods although the average frequency is exact. This pixel clock generation
system has several advantages:
• The frequency of the pixel clock can be programmed independently from the
horizontal line period.
• Since the input of the PLL is already a signal with a high frequency, the resulting pixel
frequency has an extremely low jitter.
• The resulting pixel clock follows the edge of the H-sync impulse without any delay and
always has the same quality as the sync timing of the deflection controller.