Micronas SDA 6000, User Manual

Page: 109 / 412

SDA 6000
PRELIMINARY DATA SHEET
Version 2.1
Interrupt and Trap Functions
5 - 23 Micronas
When the interrupt service routine is left (RETI is executed), the status information is
popped from the system stack in reverse order, taking into account the value of bit
SGTDIS.
Context Switching
An interrupt service routine usually saves all the registers it uses on the stack, and
restores them before returning. The more registers a routine uses, the more time is
wasted with saving and restoring. The M2 allows the complete bank of CPU registers
(GPRs) to switch with a single instruction, so the service routine executes within its own,
separate context.
The instruction “SCXT CP, #New_Bank” pushes the contents of the context pointer (CP)
on the system stack and loads CP with the immediate value “New_Bank”, which selects
a new register bank. The service routine may now use its “own registers”. This register
bank is preserved when the service routine terminates, i.e. its contents are available on
the next call.
Before returning (RETI) the previous CP is simply POPped from the system stack, which
returns the registers to the original bank.
Note: The first instruction following the SCXT instruction must not use a GPR.
Resources that are used by the interrupting program must eventually be saved and
restored, e.g. the DPPs and the registers of the MUL/DIV unit.
5.2.3 Interrupt Response Times
The interrupt response time defines the time from an interrupt request flag of an enabled
interrupt source being set until the first instruction (I1) is fetched from the interrupt vector
location. The basic interrupt response time for the M2 is 3 instruction cycles.
Figure 5-4 Pipeline Diagram for Interrupt Response Time
UED11129
IR-Flag
0
1
Interrupt Response Time
Pipeline Stage
FETCH
DECODE
EXECUTE
WRITEBACK
Cycle 1 Cycle 2 Cycle 3 Cycle 4
N
N - 1
N - 2
N - 3
N + 1
N
N - 1
N - 2
N + 2
TRAP (1)
N
N - 1
I1
TRAP (2)
TRAP
N