Micronas SDA 6000, User Manual

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SDA 6000
PRELIMINARY DATA SHEET
Version 2.1
System Control & Configuration
6 - 15 Micronas
Figure 6-2 Transitions between Idle Mode and Active Mode
Any interrupt request, whose individual Interrupt Enable flag was set before Idle mode
was entered, will terminate Idle mode regardless of the current CPU priority. The CPU
will
not go back into Idle mode when a CPU interrupt request is detected, even when the
interrupt was not serviced because of a higher CPU priority or a globally disabled
interrupt system (IEN = ‘0’). The CPU will
only go back into Idle mode when the interrupt
system is globally enabled (IEN = ‘1’) and a PEC service on a priority level higher than
the current CPU level is requested and executed.
Note: An interrupt request which is individually enabled and assigned to priority level 0
will terminate Idle mode. However, the associated interrupt vector will not be
accessed.
The watchdog timer may be used to monitor the Idle mode: an internal reset will be
generated if no interrupt request occurs before the watchdog timer overflows. To prevent
the watchdog timer from overflowing during Idle mode it must be programmed to a
reasonable time interval before Idle mode is entered.
Power Down Mode
Clocking of all internal blocks is stopped in Power Down Mode, the contents of the
internal RAMs, however, are preserved through the voltage supplied via the
V
DD
pins.
The watchdog timer is stopped in Power Down Mode. This mode can only be terminated
by an external hardware reset, e.g. by asserting a low level on the RSTIN pin. This reset
will initialize all SFRs and ports to their default state, but will not change the contents of
the internal RAMs.
SDRAM Refreshing
Before entering into one of the power save modes the external SDRAM must be put into
self-refresh-mode by use of register EBIDIR (see
Chapter 4.5 ).
UED11132
Active
IDLE Instruction
Mode
Idle
Mode
Accepted
CPU Interrupt Request
Denied
Denied PEC Request
Executed
PEC Request