Micronas SDA 6000, User Manual

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SDA 6000
PRELIMINARY DATA SHEET
Version 2.1
Peripherals
7 - 61 Micronas
Register S0BG is the dual-function Baud Rate Generator/Reload register. Reading
S0BG returns the content of the timer (bits 15 … 13 return zero), while writing to S0BG
always updates the reload register (bits 15 … 13 are insignificant).
An auto-reload of the timer with the content of the reload register is performed each time
S0BG is written to. However, if S0R = ‘0’ at the time the write operation to S0BG is
performed, the timer will not be reloaded until the first instruction cycle after S0R = ‘1’.
For a clean baud rate initialization, S0BG should only be written if S0R = ‘0’. If S0BG is
written with S0R = ‘1’, an unpredicted behavior of the ASC0 may occur during the
running of transmit or receive operations.
7.3.3.1 Baud Rates in Asynchronous Mode
For asynchronous operation, the baud rate generator provides a clock f
BRT
with 16 times
the rate of the established baud rate. Every received bit is sampled at the 7th, 8th and
9th cycle of this clock. The clock divider circuitry, which generates the input clock for the
13-bit baud rate timer, is extended by a fractional divider circuitry, which allows the
adjustment of more accurate baud rates and the extension of the baud rate range.
The baud rate of the baud rate generator depends on the following bits and register
values:
• CPU clock
• Selection of the baud rate timer input clock
f
DIV
by bits S0FDE and S0BRS
• If bit S0FDE = 1 (fractional divider): value of register S0FDV
• Value of the 13-bit reload register S0BG
The output clock of the baud rate timer with the reload register is the sample clock in the
asynchronous modes of the ASC0. For baud rate calculations, this baud rate clock
f
BR
is
derived from the sample clock f
DIV
by a division of 16.