Micronas SDA 6000, User Manual

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SDA 6000
PRELIMINARY DATA SHEET
Version 2.1
C16X Microcontroller
4 - 12 Micronas
4.3.2 General Purpose Registers
The General Purpose Registers (GPRs) use a block of 16 consecutive words within the
IRAM. The Context Pointer (CP) register determines the base address of the currently
active register bank. This register bank may consist of up to 16 word GPRs (R0, R1, …,
R15) and/or of up to 16 byte GPRs (RL0, RH0, …, RL7, RH7). The sixteen byte GPRs
are mapped onto the first eight word GPRs (see
Table 4-1 ).
In contrast to the system stack, a register bank grows from lower towards higher address
locations and occupies a maximum space of 32 Byte. The GPRs are accessed via short
2-, 4- or 8-bit addressing modes using the Context Pointer (CP) register as a base
address (independent of the current DPP register contents). In addition, each bit in the
currently active register bank can be accessed individually.
M2 supports fast register bank (context) switching. Multiple register banks can physically
exist within the IRAM at the same time. However, only the register bank selected by the
Context Pointer register (CP) is active at a given time. Selecting a new active register
bank is simply done by updating the CP register. A particular Switch Context (SCXT)
instruction performs register bank switching and automatically saves the previous
Table 4-1 Mapping of General Purpose Registers to RAM Addresses
Internal RAM
Address Byte Registers Word Register
<CP> + 1E
H
– R15
<CP> + 1C
H
– R14
<CP> + 1A
H
– R13
<CP> + 18
H
– R12
<CP> + 16
H
– R11
<CP> + 14
H
– R10
<CP> + 12
H
– R9
<CP> + 10
H
– R8
<CP> + 0E
H
RH7 RL7 R7
<CP> + 0C
H
RH6 RL6 R6
<CP> + 0A
H
RH5 RL5 R5
<CP> + 08
H
RH4 RL4 R4
<CP> + 06
H
RH3 RL3 R3
<CP> + 04
H
RH2 RL2 R2
<CP> + 02
H
RH1 RL1 R1
<CP> + 00
H
RH0 RL0 R0