Micronas SDA 6000, User Manual

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SDA 6000
PRELIMINARY DATA SHEET
Version 2.1
Sync System
9 - 7 Micronas
9.2 Register Description
SCR Reset Value: 0000
H
Bit Function
MAST Master / Slave Mode
This bit defines the configuration of the sync system (master or slave
mode) and also the direction (input/output) of the V, H pins.
0: Slave mode. H, V pins are configured as inputs.
1: Master mode. H, V pins are configured as outputs.
Note: Switching from slave to master mode resets the internal H, V
counters, so that the phase shift during the switch can be
minimized. In slave mode registers VLR, and HPR are without any
use.
VCS Vertical Composite Sync
VCS defines the sync output at pin V ( Master mode only ).
0: At pin V the vertical sync appears.
1: At pin V a composite sync signal (including equalizing pulses, H-
Sync and V-Syncs) is generated (VCS). The length of the
equalizing pulses have fixed values as described in the timing
specifications.
Note: Don’t forget to set registers VLR and HPR according to your
requirements.
INT Interlace / Non-interlace
M2 can either generate an interlaced or a non-interlaced timing. (Master
mode only). Interlaced timing can only be created if VLR is an odd
number.
0:
Interlaced timing is generated.
1: Non-interlaced timing is generated.
VP V-Pin Polarity
This bit defines the polarity of the V pin (master and slave mode).
0: Normal polarity (active high).
1: Negative polarity.
5 4 3 2 1 0 11 10 9 8 7 6 15 14 13 12
rw rw rw rw rw rw rw rw rw
- - - - COR-
BL
VSU(3..0) BLAN
KP
COR
P
HP VP INT VCS MAST