Micronas SDA 6000, User Manual

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SDA 6000
PRELIMINARY DATA SHEET
Version 2.1
Peripherals
7 - 5 Micronas
as capture or reload registers for the core timer. Concatenation of T3 with other timers
is provided through line T3OTL.
The current contents of each timer can be read or modified by the CPU by accessing the
corresponding timer registers T2, T3, or T4, which are located in the non-bitaddressable
SFR space. When any of the timer registers are written to by the CPU in the state
immediately before a timer increment, decrement, reload, or capture is to be performed,
the CPU write operation has priority in order to guarantee correct results.
Figure 7-1 Structure of Timer Block 1 Core Timer T3
The operation of the core timer T3 is controlled by its bit-addressable control register
T3CON.
Run Control
The timer can be started or stopped by software through bit T3R (Timer T3 Run Bit).
Setting bit T3R will start the timer, clearing T3R stops the timer.
UEB11195
2
n
: 1
2
n
: 1
2
n
: 1
hw_clk
f
T2EUD
T2IN
hw_clk
f
T3IN
T3EUD
T4IN
hw_clk
f
T4EUD
T3OTL
T3OTL
Control
Mode
T2
T3
Control
Mode
T4
Control
Mode
GPT1 Timer T2
U/D
Reload
Capture
GPT1 Timer T3
U/D
Capture
Reload
U/D
GPT1 Timer T4
Interrupt
Request
Interrupt
Request
Interrupt
Request