Micronas SDA 6000, User Manual

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SDA 6000
PRELIMINARY DATA SHEET
Version 2.1
C16X Microcontroller
4 - 36 Micronas
Timing
Instruction pipelining reduces the average instruction processing time on a wide scale
(usually from four to one machine cycles). However, there are some rare cases where a
particular pipeline situation causes the processing time for a single instruction to be
extended either by a half or by one machine cycle. Although this additional time
represents only a tiny part of the total program execution time, it might be of interest to
avoid these pipeline-caused time delays in time critical program modules.
Besides a general execution time description, the following section provides some hints
on how to optimize time-critical program parts with regard to such pipeline-caused timing
particularities.
4.6.2 Bit-Handling and Bit-Protection
The CPU provides several mechanisms to manipulate bits. These mechanisms either
manipulate software flags within the internal RAM, control on-chip peripherals via control
bits in their respective SFRs or control IO functions via port pins.
The instructions BSET, BCLR, BAND, BOR, BXOR, BMOV, BMOVN explicitly set or
clear specific bits. The instructions BFLDL and BFLDH allow the manipulation of up to
8 bits of a specific byte at one time. The instructions JBC and JNBS implicitly clear or set
the specified bit when the jump is taken. The instructions JB and JNB (also conditional
jump instructions that refer to flags) evaluate the specified bit to determine if the jump is
to be taken.
Note: Bit operations on undefined bit locations will always read a bit value of ‘0’, while
the write access will not effect the respective bit location.
All instructions that manipulate single bits or bit groups internally use a read-modify-write
sequence that accesses the whole word, which contains the specified bit(s).
This method has several consequences:
• Bits can only be modified within the internal address areas, i.e. internal RAM and
SFRs. External locations cannot be used with bit instructions.
The upper 256 bytes of the SFR area, the ESFR area and the internal RAM are bit-
addressable (see
Chapter 4.2 ), i.e. those register bits located within the respective
sections can be directly manipulated using bit instructions. The other SFRs must be byte/
word accessed.
Note: All GPRs are bit-addressable independent of the allocation of the register bank via
the context pointer CP. Even GPRs which are allocated to not bit-addressable
RAM locations provide this feature.
• The read-modify-write approach may be critical with hardware-effected bits. In these
cases the hardware may change specific bits while the read-modify-write operation is
in progress, where the writeback would overwrite the new bit value generated by the
hardware. The solution is either the implemented hardware protection (see below) or