Micronas SDA 6000, User Manual

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SDA 6000
PRELIMINARY DATA SHEET
Version 2.1
Interrupt and Trap Functions
5 - 27 Micronas
• If instruction N reads the PSW and instruction N-1 effects the condition flags, the PEC
response time may additionally be extended by 2 state times.
The worst case PEC response time during internal code memory program execution
adds to 9 state times (18 TCL).
Any reference to external locations increases the PEC response time due to pipeline
related access priorities. The following conditions have to be considered:
• Instruction fetch from an external location
• Operand read from an external location
• Result write-back to an external location
There are a number of combinations depending on where the instructions, source and
destination operands are located. Note, however, that only access conflicts contribute to
the delay.
A few examples illustrate these delays:
• The worst case interrupt response time, including external accesses, will occur when
instructions N and N+1 are executed out of external memory, instructions N-1 and N
require external operand read accesses and instructions N-3, N-2 and N-1 write back
external operands. In this case the PEC response time is the time needed to perform
7 word bus accesses.
• When instructions N and N+1 are executed out of the external memory, but all
operands for instructions N-3 through N-1 are in internal memory, then the PEC
response time is the time needed to perform 1 word bus access plus 2 state times.
Once a request for PEC service has been acknowledged by the CPU, the execution of
the next instruction is delayed by 2 state times plus the additional time it might take to
fetch the source operand from internal code memory or external memory and to write the
destination operand over the external bus in an external program environment.
Note: A bus access, in this context, includes all delays which can occur during an
external bus cycle.
For an EPEC request, the basic response time is 3 instruction cycles. The minimum
response time is reached when the request occurs at the end of an instruction cycle. In
this case the response time is 5 states (10 TCL). All the conditions described below that
may increase the response time apply to the EPEC.
5.2.5 Fast Interrupts
The interrupt inputs are sampled every 8 states (16 TCL), i.e. external events are
scanned and detected in timeframes of 16 TCL. M2 provides 8 interrupt inputs that are
sampled every 2 TCL, so external events are captured faster than with standard interrupt
inputs.