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SDA 6000
PRELIMINARY DATA SHEET
Version 2.1
Display Generator
10 - 41
Micronas
10.7.7
Contents of CLUT (CLR)
CLR instruction allows the contents of the CLUT1 and CLUT2 to be set.
CLR
10.7.8
Clipping Coordinates (CUR and CBR)
These GAIs are used to set clipping coordinates for memory transfers. The clipping
coordinates describe a rectangle area in the destination memory area. During a memory
transfer these ‘clipped’ memory areas are excluded from the transfer. The CUR
instruction is used to set the clipping start address. The CBR instruction is used to set
the width and height of the clipping area in amounts of pixels. A width of ‘0’ means that
no clipping is processed, a width of ‘1’ means the clipping area has the width of 1
pixel, …. A height of ‘0’ means, that no clipping is processed, a height of ‘1’ means the
clipping area has the height of 1 line, … . Next to the start address, height and width a
clipping offset must be given for clipping. For a rectangle clipping area the sum of this
clipping offset and the clipping width must be the same as the sum of the destination area
width and the destination offset. Otherwise the clipping area will be a parallelogram, not
a rectangle.
Within instruction TAR it is decided whether the clipping area is inverted or non inverted.
Thus the outside region of the defined rectangle can be used for clipping as well as the
inside region. Please also refer to
Chapter 10.5.2
.
Bit
Function
CLUT_
ADDR
(8 … 0)
CLUT address
Bits 7 … 0 are CLUT vectors of either CLUT1 or CLUT2. Bit 8 selects the
CLUT:
0:
CLUT1 (256
⌠
16 bit)
1:
CLUT2 (256
⌠
14 bit)
CLUT_
CONTENT
(15 … 0)
Contents to be written
to one of the look up tables addressed by the CLUT vector defined
above. For CLUT1 all the 16 bits are used, for CLUT2 only bits 13 … 0
are used.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CLUT_CONTENT(15..0)
0
-
-
CLUT_ADDR(8..0)
1
1
1
-
Summary of Contents for SDA 6000
Page 3: ...Contents Overview...
Page 21: ...Pin Description...
Page 22: ...SDA 6000 PRELIMINARY DATA SHEET Version 2 1 Pin Descriptions 2 3 Micronas 2 Pin Descriptions...
Page 29: ...Architectural Overview...
Page 33: ...C16X Microcontroller...
Page 88: ...Interrupt and Trap Function...
Page 122: ...System Control Configuration...
Page 159: ...SDA 6000 PRELIMINARY DATA SHEET Version 2 1 System Control Configuration 6 40 Micronas...
Page 160: ...Peripherals...
Page 282: ...SDA 6000 PRELIMINARY DATA SHEET Version 2 1 Peripherals 7 124 Micronas...
Page 283: ...Clock System...
Page 284: ...SDA 6000 PRELIMINARY DATA SHEET Version 2 1 Clock System 8 3 Micronas 8 Clock System...
Page 288: ...SDA 6000 PRELIMINARY DATA SHEET Version 2 1 Clock System 8 8 Micronas...
Page 289: ...Sync System...
Page 290: ...SDA 6000 PRELIMINARY DATA SHEET Version 2 1 Sync System 9 3 Micronas 9 Sync System...
Page 301: ...Display Generator...
Page 348: ...SDA 6000 PRELIMINARY DATA SHEET Version 2 1 Display Generator 10 50 Micronas...
Page 349: ...D A Converter...
Page 352: ...SDA 6000 PRELIMINARY DATA SHEET Version 2 1 D A Converter 11 6 Micronas...
Page 353: ...Slicer and Acquisition...
Page 381: ...Register Overview...
Page 398: ...SDA 6000 PRELIMINARY DATA SHEET Version 2 1 Register Overview 13 20 Micronas...
Page 399: ...Elelctrical Characteristics...
Page 411: ...SDA 6000 PRELIMINARY DATA SHEET Version 2 1 Electrical Characteristics 14 14 Micronas...