Micronas SDA 6000, User Manual

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SDA 6000
PRELIMINARY DATA SHEET
Version 2.1
C16X Microcontroller
4 - 31 Micronas
1st –>FETCH:
In this stage the instruction selected by the Instruction Pointer (IP) and the Code
Segment Pointer (CSP) is fetched from either the program memory, internal RAM, or
external memory.
2nd –>DECODE:
In this stage the instructions are decoded and, if required, the operand addresses are
calculated and the respective operands are fetched. For all instructions, which implicitly
access the system stack, the SP register is either decremented or incremented, as
specified. For branch instructions the Instruction Pointer and the Code Segment Pointer
are updated to the desired branch target address (provided that the branch is taken).
3rd –>EXECUTE:
In this stage an operation is performed on the previously fetched operands in the ALU.
In addition, the condition flags in the PSW register are updated, as specified by the
instruction. All explicit writes to the SFR memory space and all auto-increment or auto-
decrement writes to GPRs used as indirect address pointers are also performed during
the execute stage of an instruction.
4th –>WRITE BACK:
In this stage all external operands and the remaining operands within the internal RAM
space are written back.
A particularity of the CPU are the so-called imported instructions. These imported
instructions are internally generated by the machine to provide the time needed to
process instructions which cannot be processed within one machine cycle. They are
automatically imported into the decoding stage of the pipeline, and then they pass
through the remaining stages like all standard instructions. Program interrupts are also
performed by means of imported instructions. Although these internally imported
instructions will not be noticed in reality, they are introduced here to ease the explanation
of the pipeline in the following:
Sequential Instruction Processing
Each single instruction has to pass through each of the four pipeline stages regardless
of whether all possible stage operations are performed or not. Since passing through one
pipeline stage takes at least one machine cycle, any isolated instruction takes at least
four machine cycles to be completed. Pipelining, however, allows parallel (i.e.
simultaneous) processing of up to four instructions. Thus, most of the instructions seem
to be processed during one machine cycle as soon as the pipeline has been filled once
after reset (see
Figure 4-11 ).