Micronas SDA 6000, User Manual

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SDA 6000
PRELIMINARY DATA SHEET
Version 2.1
Interrupt and Trap Functions
5 - 20 Micronas
If a word data transfer is selected for a specific PEC channel (i.e. BWT = ‘0’), the
respective source and destination pointers must both contain a valid word address which
points to an even byte boundary. Otherwise the Illegal Word Access trap will be invoked
when this channel is used.
5.2.1 Prioritization of Interrupt and PEC Service Requests
Interrupt and PEC service requests from all sources can be enabled so they are
arbitrated and serviced (if they win), or they may be disabled so their requests are
disregarded and not serviced.
Enabling and disabling interrupt requests may be done via three mechanisms:
Control Bits allow the switching of each individual source to “ON” or “OFF” so that it may
generate a request or not. The control bits (xxIE) are located in the respective interrupt
control registers. All interrupt requests can generally be enabled or disabled via the IEN
bit in register PSW. This control bit is the “main switch” that selects whether requests
from any source are accepted or not.
For a specific request to be arbitrated the respective source’s enable bit and the global
enable bit must both be set.
The Priority Level automatically selects a certain group of interrupt requests that will be
acknowledged, disclosing all other requests. The priority level of the source that won the
arbitration is compared with the CPU’s current level and the source is only serviced if its
level is higher than the current CPU level. Changing the CPU level to a specific value via
software blocks all requests on the same or a lower level. An interrupt source that is
assigned to level 0 will be disabled and never be serviced.
The ATOMIC and EXTend instructions automatically disable all interrupt requests for
the duration of the following 1 … 4 instructions. This is useful e.g. for semaphore
handling and does not require re-enabling the interrupt system after the inseparable
instruction sequence.
Interrupt Class Management
An interrupt class covers a set of interrupt sources with the same importance, i.e. the
same priority from the system’s viewpoint. Interrupts of the same class must not interrupt
each other. M2 supports this function with two features:
Table 5-4 PEC Segment Number Register Addresses
Register Address Reg. Space Register Address Reg. Space
PECSN0 FED0
H
/ 68
H
SFR PECSN4 FED8
H
/ 6C
H
SFR
PECSN1 FED2
H
/ 69
H
SFR PECSN5 FEDA
H
/ 6D
H
SFR
PECSN2 FED4
H
/ 6A
H
SFR PECSN6 FEDC
H
/ 6E
H
SFR
PECSN3 FED6
H
/ 6B
H
SFR PECSN7 FEDE
H
/ 6F
H
SFR