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SDA 6000
PRELIMINARY DATA SHEET
Version 2.1
Interrupt and Trap Functions
5 - 10
Micronas
Note: All interrupt request sources that are enabled and programmed to the same
priority level must always be programmed to different group priorities. Otherwise
an incorrect interrupt vector will be generated.
Upon entry into the interrupt service routine the priority level of the source that won the
arbitration and who’s priority level is higher than the current CPU level, is copied into the
ILVL bit field of register PSW after pushing the old PSW contents onto the stack.
The interrupt system of M2 allows nesting of up to 15 interrupt service routines of
different priority levels (level 0 cannot be arbitrated).
Interrupt requests that are programmed to priority levels 15 or 14 (i.e., ILVL = 111X
B
) will
be serviced by the PEC unless the COUNT field of the associated PECC register
contains zero. In this case the request will instead be serviced by normal interrupt
processing. Interrupt requests that are programmed to priority levels 13 through 1 will
always be serviced by normal interrupt processing.
Note: Priority level 0000
B
is the default level of the CPU. Therefore a request on level 0
will never be serviced, because it can never interrupt the CPU. However, an
enabled interrupt request on level 0000
B
will terminate the Idle mode and
reactivate the CPU.
For interrupt requests which are to be serviced by the PEC, the associated PEC channel
number is derived from the respective ILVL (LSB) and GLVL (see
Figure 5-1
). So
programming a source to priority level 15 (ILVL = 1111
B
) selects the PEC channel group
7 … 4, programming a source to priority level 14 (ILVL = 1110
B
) selects the PEC
channel group 3 … 0. The actual PEC channel number is then determined by the GLVL
group priority field.
Figure 5-1
Priority Levels and PEC Channels
Simultaneous requests for PEC channels are prioritized according to the PEC channel
number, where channel 0 has lowest and channel 8 has highest priority.
Note: All sources that request PEC service must be programmed to different PEC
channels. Otherwise an incorrect PEC channel may be activated.
PEC Control
Interrupt
Control Register
ILVL
UED11127
PEC Channel #
GLVL
Summary of Contents for SDA 6000
Page 3: ...Contents Overview...
Page 21: ...Pin Description...
Page 22: ...SDA 6000 PRELIMINARY DATA SHEET Version 2 1 Pin Descriptions 2 3 Micronas 2 Pin Descriptions...
Page 29: ...Architectural Overview...
Page 33: ...C16X Microcontroller...
Page 88: ...Interrupt and Trap Function...
Page 122: ...System Control Configuration...
Page 159: ...SDA 6000 PRELIMINARY DATA SHEET Version 2 1 System Control Configuration 6 40 Micronas...
Page 160: ...Peripherals...
Page 282: ...SDA 6000 PRELIMINARY DATA SHEET Version 2 1 Peripherals 7 124 Micronas...
Page 283: ...Clock System...
Page 284: ...SDA 6000 PRELIMINARY DATA SHEET Version 2 1 Clock System 8 3 Micronas 8 Clock System...
Page 288: ...SDA 6000 PRELIMINARY DATA SHEET Version 2 1 Clock System 8 8 Micronas...
Page 289: ...Sync System...
Page 290: ...SDA 6000 PRELIMINARY DATA SHEET Version 2 1 Sync System 9 3 Micronas 9 Sync System...
Page 301: ...Display Generator...
Page 348: ...SDA 6000 PRELIMINARY DATA SHEET Version 2 1 Display Generator 10 50 Micronas...
Page 349: ...D A Converter...
Page 352: ...SDA 6000 PRELIMINARY DATA SHEET Version 2 1 D A Converter 11 6 Micronas...
Page 353: ...Slicer and Acquisition...
Page 381: ...Register Overview...
Page 398: ...SDA 6000 PRELIMINARY DATA SHEET Version 2 1 Register Overview 13 20 Micronas...
Page 399: ...Elelctrical Characteristics...
Page 411: ...SDA 6000 PRELIMINARY DATA SHEET Version 2 1 Electrical Characteristics 14 14 Micronas...