HP 3562A, Service Manual

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C I RC U I T D E SCR I PT IONS MO D E L 3S62A
Offset C/A Converter
U201 is a D/A converter connected to the data path at the output of amp 4 (U1 01 ) to
correct the accumulated dc offset of the ampl ifiers. This process occurs during auto zeroing.
The offset control information comes onto the board as serial data through U603, U203
and U202. U202 converts the offset DAC information to parallel format and latches it.
Over Range/Half Range Circuit
T h i s circuit compares the signal at the output of US01 (which is the s ignal .from the data
path at TP1 00, amplified X4) to a fixed voltage reference to generate the overload (OVLD)
and half range (H LFSCALE) signals. This is done with com parators USOO and US02. (Note
that the signal from US01 also leaves the board as the trigger s ignal TR IG @). The
c o mparators of USOO are configured to trigger on the positive portions of the signal as
U502 triggers on the negative. The outputs of both are wire OR'd together. The COVLD
s ig nal from the input board is OR'd with the overload signal from the ADC board so that
either cou ld activate the OVLD signal.
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Missed Sample Circuit
I f an external sample signal is used which is too fast, the MSMP s ignal is sent to the digital
fi l ter control ler. The m i ssed sample c i rcuit d igita l ly determines if the track and hold is
h o lding a signal at the time a CONY signal is received.
Diagnostic Tester
T h e ADC contro l l er (U602) is a custom b u i lt state machine. Problems with this part may
be diagnosed by using self tests which are activated by front panel key presses. Configu ra­
tion commands and test signals are sent to the ADC board as serial data through the
serial/paral lel shift register U603, so the self tests also check the CNTLDAD (contro l data)
path.
Master/Slave Selection
There is an ADC board in each analyzer input channel. These are identical boards. The
digitizing process must occur simu ltaneously on both boards, so one controller must control
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the end of conversion (EOC) and the p rocess switc h (G SW) signals to the other controll er
so it can synchronize its operations with the control l ing board. If no ADC board is instal led
in channel two, the control ler on the board in channel 1 controls its own A/D convers ion.
The slots on the mother board for the ADC boards are w ired so that the controller on
the board in channel two controls the AID conversion process on both boards. The
master/slave circuit on each board consists of an inverter (U S03d) with a p u l l up resister
on the input. The mother board connects the output of this c i rcuit of the board in the
c hannel two slot to the input of the same circ u it on the board in the channel one s lot
(they both control buffers U604 and USOS on their respective boards, too). When boards
are instal led in both slots, the board in slot two has a low level on the master/s l ave l i ne
which feeds the input of the inverter on the board in slot one, resu lting in its master/sl ave
I ine being high. When the channel two ADC board slot is empty the ADC board in channel
one automatical ly becomes the "m aster"; it takes control of its own conversion process.