HP 3562A, Service Manual

Page: 338 / 570

MOD E L 3562A C I RC U I T D E SC R I PT I O N S
6-16 A33, A3 5 INPUT
The input assembly (along with the ADC) implem ents the voltage, ranges and cond itions
the input signals. The input overload detect circuit warns the operator that the reference
voltage is excessively high. The common mode rejection DAC compensates for differences
between the H IG H input and the LOW input circu its.
The block d iagram of the input assembly is shown in figure 6-A33. The HP 3562A has two
channels of balanced d ifferential inputs; the A33 I nput assembly is identical to the A35
I n put assem bly. Each assembly has a H IG H input and a LOW input. The H I G H input is
the chan nel's BNC center conductor and the LOW input is the channel's BNC she l l
conductor. The H I G H and LOW input signals are attenuated by a ladder attenuators. The
input attenuators use resistors for low frequency attenuation and adj ustable capacitors
for high frequency flatness response. An internal analog s ignal (ST I M @ ) from the A30
Analog Source assembly is put into the H I G H signal path. The instrument uses this signal
for self-tests and calibration.
After the signal is attenuated, it goes into a buffer. The buffer's power suppl ies are
bootstrapped to al low for a 20V common mode signal. After the H I G H input and LOW
input signals are attenuated and buffered, they are subtracted using a d ifference amplifier.
'The output of the difference amplifier is sent to a times three ampl ifier which is adjustable
for gain and de offset.
After the difference ampl ifier, three attenuator/gain stages provide the 2 d B intermediate
gain and attenuation steps. One of the stages is on the input assembly and the other two
stages are on the ADC assemb ly. E ach stage contains a m u ltiplexer and a times three
ampl ifier.
The input assembly is control led by two serial-in parallel-out shift registers and rel ay d rive
c i rcu its. The serial control data word (CNTLD) from the A1 Digital Source is shifted into
the registers and then the output is latched by the load channel signal (LDCH L). This control
word determines which of the relays are set, the settings for the m u ltiplexers in the
attenuator/gain stages, the common mode rejection DAC output val ue, and the de offset
value (ci rcuit on the ADC assembly). The input sends the ADC its control data word (CNTLD
AD) from the interface shift registers.
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