HP 3562A, Service Manual

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C I RC U I T DESCRI PT IONS MOD E L 3562A
CAS L L
Col umn address strobes. Clock the mu ltiplexed add ress into the
CASU l
dynam ic RAMs.
C lK
8 MHz clock. The 8 MHz system clock used to synchronize the global
RAM board to the system C P U .
C D
Chip disable. Tu rns the global b u s transceivers on (Iow) a n d off (high).
C O U N T E N l
Count enab le, active low. Increments the memory address cou nter and
decrements the memory word cou nter for each word transfer to the
disp lay.
01 5
Set data bit 1 5. Set by the system CPU at the start of a new frame.
Sets the ARML signal to clear the display refresh tim er.
OAMUXl
D isab le add ress m u ltiplexer, active low. Opens the output of the
add ress m u ltiplexer so that the refresh add ress cou nte r can be used
for setting the gl obal add ress li nes. This is the i nverse of the arbiter
circuit signal YD, which i n d icates a memory refresh grant.
G O O
G lobal data li nes between dynam ic memory a n d global bus
through
transceivers.
GD1 5
GSMP
Global sample. A 4.26 MHz clock produ ced by the delay l i ne timer
and used as the c lock for the synchronizing register.
I D lH
Idle, active low. E nsures that global RAM does not change when there
is no memory grant asserted.
MAO
Memory address bus l i nes 0 through 7.
through
MA7
MCAS
Master col umn (row) address strobe. Tim ing signals to the memory
grant, display, active low.
MGRFS H l
M R B2D2
M RRFSH
PWRO N
RAM G R/GWl
6-70
Memory grant, memory refresh, active low.
Memory request, display.
Memory req uest, memory refresh.
Power on. Signal f rom system CPU to global timing circuit to ensure
global tim ing is initial ized at correct frequency.
RAM global read/global write, active low. Triggers the global bus
tranceivers. When low, the transfer -is a write cycle. When high, the
transfer is a read cycle.