HP 3562A, Service Manual

Page: 272 / 570

MOD E L 3562A
C I RC U I T D E SC R I PT I O N S
The
counter read/write contro l
(A6U1 07) controls timing for data transfer between the
U 1 09 cou nter and the local data bus. U1 07 is held in a clear state u ntil the system CPU
activates the cou nter select signal (COUNTERSE LH). Operating as a sh ift register, U1 07
d rives the chip select (CS) cou nter i n put and the NAND gates driving the read and write
i nputs to the cou nter. After four clock cycles of delay, the proper configu ration signals
cause the cou nter to write to or read from the local data bus.
System
System
Data
Data
Bus
Bus
Interface
To CPU
I RQTSL
To Kybd
Trigger
LED
Control
Digital Source
System
System
Address
Address
Bus
Decoder
Figure 6-ASd A6 Block Diagram
I nterrupt
Control Lines
Counter DT ACK
To
I
From AS
,
LO Local Control
Select, Data Lines
Bus
Data
Point
Measurement
Counter
Controller
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