HP 3562A, Service Manual

Page: 287 / 570

MOD E L 3S62A
C I RC U IT DESC R I PT I O N S
6-9 AS, GLOBAL RAM/DISPLA Y CONTROL
A 1 7, DISPLAY INTERfACE
The global RAM board stores data and arbitrates access to memory. It also works with
the display interface board to control the transfer of data from memory to the display.
Refer to the block diagrams in figures 6-A8a and 6-A8b and the schematic in figu res 9-A8a
and 9-A8b as referenced in the fol lowing circuit descriptions.
Arbiter
The arb iter section controls access to global RAM. Seven devices send memory req uest
signals to the arbiter. The synchronizing register (U507) syn chronizes the signals com i ng
onto the board with respect to the' global RAM. The priority decoder (US06) samp les the
m emory requests period ically and allocates memory cycles based on the fol lowing priority
l ist:
1 .
FFT, A9
2 . D F1 (Digital Fi lter Channel 1 ), AS
3 . D F2 (Digita l Filter Channel 2), AS
4. RFSH (Memory Refresh), A8
5 . B2D2 (Display I nterface), A1 7
6.
FPP, A7
7. 68 (System CPU), A2
8 . I d l e (If n o device has asserted a memory request, the memory/global bus
transceivers are disab led to p revent memory access.)
The feedback network (U40S, U407, U408, and U S08) prevents any device from receiving
two consecutive memory cyc les. The only exception is the FPP, which is allowed two
consecutive memory cycles if no higher priority device is requesting memory.
A two-wi re handshake coordi nates memory req uests and grants. When a device wants
memory access, it f i rst sets up val id global add ress and data at its output bus d rivers.
T he device then in itiates handshak ing by asserting its memory request l i ne low. When
the device is ai located a memory cycle, its memory grant line goes low. This signal enables
the device's add ress and data bus drivers. The add ress flows to the global RAM add ress
. .
...... . .. ' �
val id data is on the bus. The memory grant unasserts and the handshake is ended.
Global Timing
The global timing section consists of a delay l ine osc i l l ator and gating logic. Three delay
l ines (U31 1 , U31 2, and U41 1 ) each have ten taps, each tap delayed 1 0 ns from the previous
tap. The output from the thi rd tap of the th i rd del ay l ine feeds back through an inverter
to the input of the fi rst delay l i ne. The pol arity of the s ignal changes every 235 nsec
(230 nsec through the delay l ines p l u s S nsec through the inverter). The res u lt is a 2.1 3
MHz square wave. This signal is tapped at several intervals along the delay lines and passed
through com binations of logic gates to generate t i m i ng s ignals.
6-67