HP 3562A, Service Manual

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MO D E L 3562A
C I RC U IT D E SCR I PT I O N S
C LOCK G E N E RATOR
The clock generator creates two complementary clock pulses from the 1 0.24 MHz system
c lock. This circu it prod uces an eight volt peak pu lse signal for use in the d igital fi lter
ICs. This pu lse must drive a high capacitance and sti l l reach approximate ly eight volts.
OVE RLOAD DET ECT
The first three bits in the ADC serial data stream contain overrange i nformation from the
A DC converters. This information is stri pped off the serial data stream by the d igital filter
control IC and processed by the ADC overload detect l e . The overload i nformation is
then sent to the digital filter control IC and incl uded in the status information given to
the system CPU.
LO S I G NAL/CON STANT SE LECT
The local oscillator/constant select circuit mu ltip lexes the S I N E and COS I N E signals from
the LO board to the CH1 and CH2 digital fi lter fu nctional blocks. In baseband operation,
a constant is output by activating C H 1 LOS E L and C H 2 LOS E L signals.
D I G ITAL F I LT E R/LOCAL DATA BUS I NT E RFACE
The digital fi lter/local data bus interface isolates the digital fi lter bus from the local data
bus. The information passing through these ICs consists of configu ration commands from
the system data bus to the digital filters and status i nformation from the d igital filters
to the system data bus.
F I LTER CONTROL
The fi lter control block controls data flow for the three digital fi lter modes . When a filter
control ler IC has data ready to store i n global RAM, it requests the global bus by activating
the CHxBRy signal, where x corresponds to input channel nu mber (1 or 2) and y corresponds
to the channel mode nu mber (1 , 2, or 3; see D I G ITAL F I LT E R description). A5U205 and
A6U206 enable oniy the channei and mode for which access to the giobai bus has been
requested and granted.
The global bus DMA control and paral lel input control block is composed of several smal ler
blocks. The function of these blocks is exp lained in the fol lowing discussion.
The
DMA add ress decoder
(A5U505) receives add resses from the system add ress decoder
on the A6 Digital Fi lter Control ler board. These add resses and the MYAD DR contro l l i ne
are decoded to generate filter channel write control, channel output strobe, and read status
signals.
The
DMA pointer register
(A5 U31 1 ) latches into the DMA control ler ICs (A5 U307, A5U309)
the address of an internal DMA Control ler register that is to be loaded with i nformation.
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