MOD E L 3562A
REQG B l
lDG D B R l
B I0320l
IRQ320l
B RDSE lH
C I RC U I T D ESCRI PT I O N S
Request global bus, active low. A signal from the I/O seq uencer to the
sequence decoder and the global bus handshake circ u it req uesting control
of the global bus.
Load global data bus register, active low. T h is signal loads data from the
global data bus into the read registers. It is activated when the FFT is granted
memory access and G DS L (global data strobe) becomes active (Iow) ..
Branch on I/O, active low. A signal from the test bit mux to the TMS320
m icroprocessor.
I nterrupt request to the TMS320 microprocessor, active low.
Board select, active h igh. Signal created by the identity comparator in the
FFT interrupt circu it. This signal indicates that the system CPU is add ress
ing the FFT board.
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Summary of Contents for 3562A
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Page 16: ...GEN ERAL INFORMATION MODEL 3562 T bJe 1 3 Specifications cont 1 10 ...
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Page 207: ...MODEL 3562A CR Cl ...
Page 209: ...MODE L 3562A Cl ...
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Page 213: ...r A1 a pQWERSuP PLY I 03562 66518 REV A REV 8 8MPOUT 58 58 FRONT REAR P ANEL ii O N ...
Page 214: ... C401 8S1 15ISI t 1 J400 ...
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Page 224: ...A3 CQVLCLI A3 ...
Page 231: ...S V InO 3J nOS N I l3 3 1 1 1X3 NI 31dWVS lX3 H l 1 3 NNVH I 0 Ioe J ...
Page 237: ...Sample Clock SAMP DS DATA oe _ _ _ _ _ BUS NOTE FULL SPA BASi BAI MODE ...
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Page 259: ...WRITEL A22L l cc E Vl 8 MHz A23L ASL Inverting A1L A21 L D rivers r ...
Page 305: ...c c I O Sequencer S r J Sequence Decoder ...
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Page 324: ...EXT TRIGGER TRIG 1 TRIG 2 CALTRIG CNTLD COMI W CNTCLK LDTRGL RESETL ...
Page 327: ... RH r I N EXT BUFFER SAMPLE _ _ _ IN ...
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