HP 3562A, Service Manual

Page: 297 / 570

C I RC U IT D ESCR I PTIONS
MOD E L 3562A
SYSTEM ADDRESS BUS BUFFE R
T h e system add ress bus buffer (U505) appears as a read-only port to the TMS320 system.
This register is used to tel l the TMS320 processor which port the system CPU wants to
access on the FFT board. These ports exists as RAM registers inside the TMS320.
SYSTEM DATA BUS I NTE RFAC E
The system data i nterface (U 506-U509) appears as one read-only register and one w rite­
o n ly register to the TMS320 system. Each is activated by the FF port decoder. These registers
are used to transfer data between the FFT board and the system CPU (A2).
F FT INTERRUPT
The FFT board is control led and mon itored by the system CPU through the use of pseudo­
registers i nside the TMS320 i ntegrated c ircuit. When the system CPU executes a write or
read to one of these ports, the interru pt circuit on the FFT board generates an i nterrupt
s ignal which is sent to the TMS320.
The FFT interru pt circuit consists of an identity comparator connected directly to the in­
coming system address bus. When the system CPU add resses the FFT board, the identity
com parator (U51 0) in the interru pt block activates the BRDSELH (board select, active high)
wh ich generates an i nterru pt for the TMS320.
To determine which (pseudo) register the system CPU is requesting access to, the FFT inter­
r u pt service routine reads the add ress bus (th rough the address bus buffer, U505) onto
the internal data bus. When the address is read, the interru pt is cl eared and the data is
transferred i n the appropriate d i rection through the system data bus.
I f the CPU is writing to the FFT board, the TMS320 reads the data registers by asserti ng
the SDBUS I N L (system data bus in) signal which activates DTAC KL (data acknowledge).
W hen the system CPU receives the DT AC K L s ignal, it removes (or changes) the add ress,
which deactivates BRDSE LH, which deactivates DT ACKL. If the FFT is writing to the C P U ,
t h e FFT puts the data on the output data iegisteiS ( a wiite operation) and performs a
(d u m my) read to activate DTACKL, tel l ing the CPU that the data on the bus is val id. When
the CPU fin ishes reading the data it
_ _ _ _ .
.
.
-
.
.... .
�.::
..
"'.�; ..
;
�
.
6-78
C P U I NT E RRUPT
T h e CPU interru pt circu it consists of an R-S f l i p-flop with two Reset in puts and one Set
i nput. I nverters are used in pairs to ensure a single TTL load on the system bus. The R E S E T L
s i gnal from the system resets the CPU interrupt circ u it to ensure that the FFT board does
not have an i m pend ing interru pt requ est after a reset.
The FFT performs a CPU interrupt by activating the SI RQSYSL (set interru pt request, system)
l ine which activates I RQT4L on the system bus. When the system CPU ru n s its i nterrupt
service routine, it reads the status register on the FFT board and the TMS320 resets the
i nterrupt.