MOD E L 3562A
C I RC U I T DESC R I PT I O N S
5. The FPP fetches a 32 bit comm and using the Y bus and corresponding global bus
registers.
6 . The ALUs read and store the address of the data block to be operated on.
7. The instruction mapping PROM i nterprets the com mand data on the Y bus and tel ls
the sequencer where to start its add ress sequence.
8. The seq uencer addresses the m icrocode memory using the pipeline add ress bus.
9. The m icrocode memory sends the appropriate instruction to the ALUs using the
A and B port add ress and ALUs i nstruction bus.
1 0. The designated instruction is performed.
1 1 . When fin ished with a command (or an error is detected), the FPP sends an i nterrupt
(l RQT3 L) to the system CPU.
1 2. Steps 8 through 11 are repeated until the computation is com pleted. This process
incl udes instructions for fetching data blocks from global RAM.
1 3. The result of the computation is stored in global RAM at an address previously specified
i n the comm and stack.
1 4. The FPP fetches the next command stack.
1 5. Steps 5 through 1 3 are repeated u ntil all the command stacks are done (u n l ess the
FPP is reset or an error is detected by the condition code multiplexor).
1 6. The sequencer add resses the m icrocode memory for the 'wait' command.
1 7. The wait command is executed using the constant pipe l i ne interface. The FPP remains
i n a wait loop u ntil the next com mand add ress flag (ADDFLG) is sensed.
System Address Decoder and Handshake
operations.
comparator asserts
the My Add ress signal (MYADDRSL) to activate the address PAL. The address PAL activates
the fol lowing signals:
1 . Add ress Flag (AD D FLG)
This signal latches the system data bus into the command pointer registers. (Th is d ata
is the starting add ress of the comm and stack i n global RAM.)
2. Data Acknowledge (DT ACK)
DT ACK is retu rned to the system C PU to indicate the com pletion of the FPP handshake.
3. Cond ition Code (CCOD E)
CCOD E is sent to the sequencer. When the sequencer receives CCODE, it branches
out of wait loop and starts the FPP process.
6-5 9
Summary of Contents for 3562A
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Page 237: ...Sample Clock SAMP DS DATA oe _ _ _ _ _ BUS NOTE FULL SPA BASi BAI MODE ...
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Page 259: ...WRITEL A22L l cc E Vl 8 MHz A23L ASL Inverting A1L A21 L D rivers r ...
Page 305: ...c c I O Sequencer S r J Sequence Decoder ...
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Page 324: ...EXT TRIGGER TRIG 1 TRIG 2 CALTRIG CNTLD COMI W CNTCLK LDTRGL RESETL ...
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