HP 3562A, Service Manual

Page: 266 / 570

MOD E L 3S62A
C I RC U I T DESCR I PT I O N S
6-7 AS, DIGITAL FILTER
A6, DIGITAL FILTER CONTROLLER
The d igital filter assembly (D FA) consists of the digital filter board (AS) and the digital
filter control ler board (A6). The d igital fi lter processes two channels of serial data from
the instru ment front end (ADC boards) and stores the resu lts in global RAM. Processing
consists of convers ion from a serial format to a parallel format and, if requ i red, digital
filtering or zoom (a combination of frequency shifting and fi ltering). The processed data
is transferred on the global data bus to G lobal RAM (A8).
Data Flow
Refer to the block diagram in figure 6-ASa. Two data signals, one from each in put, come
onto the AS board in a serial format from the A32 and A34 ADC boards. These signals
enter the digital fi lter blocks where they are processed .
A4
I
LO I sin
BD
I
cos
I
A32 Serial
A34 ADC
I
Data
BD
From
I
ADC 1 & 2
I
I
I
I
A2
Sys Adr Bus
CPU
BD
Sys Data Bus
I
I
I
I
AS
I
Digital
----
Fiit�;
----
Global Bus
Local
I
Data
I
Control
Bus
Lines
I
I
A6
I
Filter I
Control
I
Filter can pass d
to RAM without filt
ata
ering.
ter it and pull it out & fil
later.
A8
RAM
Figure 6-ASa System Block Diagram Referenced to the Digital Filter Boards
In to d igital fi lter at a 10.24 MHz rate. The data
is reclocked by AS U S1 2. The fi lter accepts one input data word and sends the SYNC2
pu lse to the A4 Local Osc i l l ator and A6 Digital Filter Control boards.
Measurem ent data is in put serially to a filter control ler. I ncom ing data is processed in
one of three ways:
Strea ming
If V I EW T I M E is selected with a span of 1 00 kHz or V I EW I N PUT is
active, processing consists only of conversion to a paral lel format for
storage in G l obal RAM.
6-45