HP 3562A Service Manual Download Page 316

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Summary of Contents for 3562A

Page 1: ... changes are made in the instru ment to improve per formance and reliability the appropriate pages will be revised to include this information I WARNING To prevent potential fire or shock hazard do not expose instrument to rain or moisture Manual Part No 03562 9001 0 Microfiche No 03562 9021 0 Copyright 1985 Hewlett Packard Company 8600 Soper Hill Road Everett Washington 98205 1298 USA Printed Sep...

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Page 3: ...lammable gases or fumes Operation of any electrical instru ment in such an environment constitutes a definite safety hazard KEEP AWAY FROM LIVE CIRCUITS Operating personnel must not remove instrument covers Component replacement and internal adjustments must be made by qualified maintenance personnel Do not replace components with power cable connected Under certain conditions dangerous voltages m...

Page 4: ... in case of a fault A terminal marked with this symbol must be con nected to ground in the manner described in the installation o perat ing manual and before operating the equipment Frame or chassis terminal A connection to the frame chassis of the equipment which normally includes all exposed metal structures Alternating current power line Direct current power line Alternating or direct current p...

Page 5: ... Considerations 1 5 1 7 G rounding 1 6 1 8 Operator Maintenance 1 6 1 9 Specifications 1 7 1 10 Recommended Test Equipment 1 1 1 Number 1 1 1 2 1 3 1 4 Number 1 1 1 2 1 3 1 4 Tables Title Manual Section Descriptions HP 3562A Options Specifications Recommended Test Equipment Figures Title HP 3562A Front and Rear Views Accessories Supplied with the HP 3562A Input Connections Constructing a Feedthrou...

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Page 7: ...fix separated by a letter designating the country in which the instrument was manufactured A USA G West Germany J Japan and U United Kingdom The prefix is the same for all identical instruments and changes only when a major instru ment change is made The suffix is unique to each instrument The contents of this manual apply directly to instruments having the same serial number prefix as listed on t...

Page 8: ...T FUSE 1I5V NORMAL SLD 6A 2S0V 230V NORMAL BLO 3A1250V WARNING FOR CONTINUED PROTECTION AGAINST FIREHAZAAD REPLACe ONLYWITH THE SAME TYPE AND RATING Of FUSE AS FleoFOR THE UNE AND VOLTAGE BEING CHANNEL 1 _____ e ___ OV RRANGE ___ e e 0 o o o DISPLAY OUTPUT X Y Z FUSE LINE 115V _25 10 48 440Hz 450VAMAX REF IN EXT SAMPLE IN SYNC OUT 230V 15 10 lS 66Hz 450VAMAX X RAYS GENERATED IN THISINSTRUMENTARE S...

Page 9: ... 20 0698 Line 2 240 V 6A Neutral Earth Line PLUG SEV 1 01 1 1 959 24507 TYPE 1 2 CA BLE H P 81 20 2104 240 V OPERATION PLUG NZSS 1 98 AS C1 12 CABLE HP 81 20 0696 PLUG NEMA 5 1 5 P CABLE HP 8120 1521 PLUG CEE7 V11 CA BLE HP 81 20 1 692 PLUG DHCR 1 07 CABLE HP 81 20 2956 The number shown for the plug is the industry identifier for the plug only Line 240 V OPERATION Earth Line Neutral 120 V 6A Neutr...

Page 10: ...ignators Ordering information is also included V BACKDATING This section lists the information required to adapt this service manual to instruments manufactured prior to the printing of this manual VI CIRCUIT This section contains the HP 3562A theory of operation DESCRIPTIONS the signal name descriptions and circuit board block diagrams Use this section to understand how the H P 3562A s circuits f...

Page 11: ...provides the flexibility to manipulate the gathered data into almost any format required through waveform math frequency response syn thesis and curve fitting routines The HP 3562A also directly drives HP GL plotters without a controller External disc drives can be directly driven for data and instrument state storage 11 5 OPTIONS There are five options available for the HP 3562A They are availabl...

Page 12: ...rts inside the HP 3562A Only trained service personnel should perform instrument repairs I WARNING To avoid serious injury disconnect the ac line power cord before removing or installing the ac line fuse Voltage settings There are two voltage settings on the rear panel of the HP 3562A Before connecting the line power cord or turning on the instrument verify the voltage selector switch is in the co...

Page 13: ...the instrument by giving typical but non warranted per formance specifications Supplemental characteristics are denoted as typical nominal or approximately Table 1 3 Specifications FREQUENCY Measurement Range 64 JLHz to 100 kHz both channels single or dual channel operation Accuracy 0 004 of frequency reading Resolution Span 800 both channels single or dual channel operation Spans Baseband Zoom of...

Page 14: ...nel BNC Connector Input Signal Case 3 Case 4 Input Signal A j rv BNC Connector JInput Channel Input Signal B rv Cases 3 and 4 are input connections which degrade alllJJllLUue accuracy For these cases the ampl itude accuracy on viouslv specified must be modified with the accuracy adders paragraph Figure 1 3 Input Connections ...

Page 15: ...80 dB below full scale input range 1 6 averages 10 kO termination PHASE Accuracy Single Channel input connections as specified in Cases 1 and 2 in figure 1 3 10 kHz 10 kHz to 100 kHz INPUTS Input impedance 1 MO 5 shunted by 100 pF 2 5 12 0 Input Coupling The inputs may be ac or dc coupled ac rolloff is 3 dB at 1 Hz Crosstalk 1 40 dB 500 source 500 input termination input connectors shielded Common...

Page 16: ...GEN ERAL INFORMATION MODEL 3562 T bJe 1 3 Specifications cont 1 10 ...

Page 17: ...0 RECOMMENDED TEST EOUIPMENT The equipment required to maintain the HP 3562A is listed in table 1 4 Other equipment may be substituted for the recommended model if it meets or exceeds the listed critical specifications When substitutions are made the user may have to modify the performance and adjustment procedures to accommodate the different operating characteristics Resistance Tolerance Power 1...

Page 18: ...00V 0 1 1 MO input impedance dc Voltage 1V to 1 000V 0 1 Frequency Range 1 Hz to 1 00 kHz HP 339A Ampl itude Range 0 1 V to 1 Vrms Alternative Distortion 5 80 dB 0 01 H P 3326A Bandwidth 50 MHz H P 1 980B Two Channel External Trigger Alternative HP 1 740 Maximum Clock 25 MHz HP 5006A Clock Set up Time 20 ns Alternative HP 5005A H P 5005B Voltage Range 80 to 120 Vac Frequency Range 60 Hz Voltage Ac...

Page 19: ...Input Analog Ext Brd H P 03562 66542 Common Mode Cable HP 03562 61 620 Input Extender Cable H P 03562 61 621 5MB to BNC adapter cable HP 03585 61 61 6 50 1 at dc H P 11 048C Alternative H P 10100C 600 1 at dc H P 11095A BNC to BNC length S30 cm H P 81 20 1 838 Alternative H P 11170A BNC female to Banana male Pomona Elect Model 1296 BNC f to dual banana male HP 1 251 2277 BNC Tee m f f H P 1 250 07...

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Page 21: ...ous Signal Level 2 21 Source Amplitude Accuracy and Flatness 2 25 Operation Verification Test Record 2 27 PART B PERFORMANCE TESTS Introduction 2 29 How to Use Part B 2 29 Required Test Equipment 2 30 Initial Equipment Setup 2 30 Self Test 2 31 DC Offset 2 31 Amplitude Accuracy and Flatness 2 34 Amplitude Linearity 2 39 Amplitude and Phase Match 2 42 Anti Alias Filter Response 2 48 Frequency Accur...

Page 22: ...p 2 7 OV Amplitude and Phase Match Test Setup 2 10 OV Frequency Accuracy Test Setup 2 13 OV Common Mode Rejection Test Setup 1 2 15 OV Common Mode Rejection Test Setup 2 2 17 OV Single Channel Phase Accuracy Test Setup 2 19 OV Noise and Spurious Signal Level Test Setup 2 21 Marker Positions 2 29 DC Offset Test Setup 2 32 Amplitude Accuracy and Flatness Test Setup 2 35 Amplitude Linearity Test Setu...

Page 23: ...epair inspections The completion of all the per formance tests verifies that the HP 3562A conforms to its published specifications One or more of the performance tests should be done after some repairs Refer to Service Section VI I I for this information Note Tables and figures beginning with OV are used in the operational verifica tion tests 2 2 CALIBRATION CYCLE To verify that the HP 3562A is me...

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Page 25: ... keys and soft keys In this section the hard keys are in bold text and the soft keys are in regular text For example FREQ FREQ SPAN 10 kHz This example instructs you to press the hard key FREQ and the soft key FREQ SPAN After pressing the soft key FREQ SPAN enter 10 kHz 3 Refer to figure 2 1 for the position of the X and Y marker readings 4 Record the results of each of the operational verificatio...

Page 26: ...ent of table 1 4 is used to complete the operational verification the instruments listed below must be set to the preset conditions listed before beginning the test In each test any unspecified parameters should be set to the follow ing conditions HP 3325A frequency synthesizer Function SINE WAVE Frequency 1 kHz Amplitude 1 mVrms Phase o Degrees dc Offset OV Modulation OFF Sweep OFF Fluke 5200 ac ...

Page 27: ... SELF TEST PASSES is displayed in the lower right corner of the display check PASS on the Operational Verification Test Record If Test Fails Go to Fault Isolation Section Section VI I 2 8 DC OFFSET This test measures the level of the dc offset generated with auto cal on Requ ired Test Equipment 2 son feedthrough terminations D M DDD 0 00000 0 HP 11048C Gl QQD_DDD DD 000 8 DD gJ 00 BOO DDD BBBG ggg...

Page 28: ...RM 2 STABLE 1 kHz P SPEC UN ITS X VALUE 51 dBVrms ENTER VOLTS RMS VOLTS o Hz C Record the Ya marker reading on the Operational Verification Test Record for the CHAN 1 measured value D Record the Yb marker reading on the Operational Verification Test Record for CHAN 2 measured value If Test Fails Check Adjustments Section I I I Troubleshooting Section VII I Track and Hold Offset Adjustment Input DC...

Page 29: ...OR FLUKE 5200A REAR PANEL VIEW D FRONT PANEL VIEW PHASE LOCK INPUT 0 C i 0 0 0 0 0 0 o HP 3325A Fluke 5200A FREQUENCY SYNTHESIZER HP 3325A I I c J C J 1m m m W 81 00000 1 11G m m m m 1 m m m 88 88888 I J J o C J 00000 m il BNC CABLE 8120 1B40 I HP 3562A 11 11 g8 mooO QJ G J J OUTPUT J7 L if TEE BNC OUAL BANANA 13 F TO 11001 60001 1250 BANANA BANANA Figure 2 3 OV Amplitude Accuracy and Flatness Tes...

Page 30: ...s C Press the HP 3562A keys as follows PRESET CAl WIN DOW AVG U N ITS A B RESET SINGLE CAL FLAT TOP 4 STABLE P SPEC UNITS Table 2 1 CV Amplitude Accuracy and Flatness HP 3562A Range Signal ac Calibrator Setting Frequency Amplitude 9 dBVrms 1 kHz 2 81 84 Vrms 9 dBVrms 99 kHz 2 81 84 Vrms o dBVrms 1 kHz 1 0000 Vrms o dBVrms 99 kHz 1 0000 Vrms 13 dBVrms 1 kHz 22387 Vrms 1 3 dBVrms 99 kHz 22387 Vrms E...

Page 31: ...A keys as follows START SPCL MARKER MRKR PEAK To signal frequency in table 6 Record the Ya marker reading on the Operational Verification Test Record for CHAN 1 7 Record the Yb marker reading on the Operational Verification Test Record for CHAN 2 If Test Fails Check Adjustments Section I I I Troubleshooting Section VI I 2nd Pass Gain Adjustment ADC Offset and Reference Adjustment Input Flatness Ad...

Page 32: ... Equipment BNC Tee HP 1 250 0781 HP 3562A BNC CABLE B120 1840 I_ BNC CABLE B120 1838 TEE 1250 0781 F TO F BARREL 1250 0080 Figure 2 4 aV Amplitude and Phase Match Test Setup Procedure A Connect the HP 3562A as shown in figure 2 4 The cables to channel 1 and channel 2 must be the same length B Press the HP 3562A keys as follows PRESET CAL INPUT COU P LE RESET SINGLE CAL CHAN1 AC CHAN2 AC GROUND CHA...

Page 33: ...ANGE 47 dBVrms SOURCE SOURCE LEVEL SCALE Y FIXD SCALE START Y 1 1 dB ENTER 375 100 kHz 49 dBVrms 2 2 dB 2 If the measurement is within the marker band check PASS on the Operation Verification Test Record for part 1 3 Press the HP 3562A keys as follows RANGE o dBVrms SOU RCE SOURCE LEVE L o dBVrms START y 1 1 dB 4 If the measurement is within the marker band check PASS on the Operation Verification...

Page 34: ... Press the HP 3562A keys as follows RANGE SOU RCE COORD START SCALE y 47 dBVrms SOURCE LEVEL PHASE Y FIXD SCALE Y VALUE 49 dBVrms 1 1 Degree 5 5 Degree 2 If the measurement is within the marker band check PASS on the Operation Verification Test Record for part 4 3 Press the H P 3562A keys as follows RANGE o dBVrms SOU RCE SOURCE LEVEL o dBVrms START y Y VALUE 5 5 Degree 4 If the measurement is wit...

Page 35: ...stments Calibrator Adjustment A33 A35 I nput Boards Troubleshooting Section VI I A32 A34 Analog Digital Converter Boards A30 Analog Source Board 2 1 1 FREQUENCY ACCURACY This test measures the frequency accuracy of the HP 3562A Required Test Equipment Frequency Synthesizer son feedthrough termination FREQUENCY SYNTHES I ZER HP 3325A J 1 ffiJ 0 0 0 88 o 0 1 0 0 DODO w 110 0 0 0 0 1 88888 li lil 000...

Page 36: ...Frequency Synthesizer Frequency Amplitude Function 99 kHz 1 Vrms Sine Wave C Press the HP 3562A keys as follows PRESET CAl RANGE FREQ AVG START x RESET SI NGLE CAL o dBVrms CENTER FREQ 2 STABLE 99 kHz ENTER D Record the X marker reading as the measured value on the Operational Verification Test Record If Test Fails Check Adjustments Section I I I Troubleshooting Section VI I 20 48 MHz Reference Ad...

Page 37: ...gle channel Requ ired Test Equipment Frequency Synthesizer Common Mode Cable FREQUENCY SYNTHESIZER HP 3325A I I IT J m IDDDDll rn1000001 00 88 ggggg 0 o 00000 0 0IIJ BNC BNC B120 1840 HP 3325A HP 03562 61620 HP 3562A 11 I 000 8 DDD gJ 000 DDD 000 0 0 000 ODDDD ooo Q ODDDD M W L I ALLIGATOR ALLIGATO TEE F T BNC CABLE 8120 1838 1250 0781 o F BARREL 0080 1250 Figure 2 6 QV Common Mode Rejection Test ...

Page 38: ...SET CAl AVG WIN DOW A B U N ITS RESET SINGLE CAL 1 6 STABLE FLAT TOP P SPEC UNITS Table 2 2 CV Common Mode Rejection Signal Signal Range Amplitude Frequency Setting 1 5 680 Vrms 66 Hz 1 6 dBVrms 3 41 3 Vrms 500 Hz 11 dBVrms Range Setting 2 8 dBVrms 1 2 dBVrms ENTER VOLTS RMS VOLTS Specification 80 dB 65 dB D For each of the frequencies listed in table 2 2 perform steps 1 through 9 1 Set the Freque...

Page 39: ...d as the first measurement for CHAN 1 4 Record the Yb marker amplitude reading on the Operation Verification Test Record as the first measurement for CHAN 2 FREQUENCY SYNTHESIZER HP 3325A I m 8 8 8 88 o 8 00000 00000 00000 00000 I tIJ 8 I 11 8 8 8 8 1 8 III BNC BNC B120 1B40 HP 3562A 0 rgg Gl muJ G M WW o 0 000 000 rj L J 7 TEE COMMON MODE F TO HP 03562 61620 1250 Figure 2 7 CV Common Mode Rejecti...

Page 40: ...econd measurement for CHAN 2 9 Calculate the relative value for both channels First Measurement Second Measurement Relative Value If Test Fails Check Adjustments Section I I I Troubleshooting Section VI I Input dc Offset Adjustment Calibrator Adjustment A33 A35 Input Boards A30 Analog Source 2 1 3 SINGLE CHANNEL PHASE ACCURACY This test measures the phase accuracy of the HP 3562A relative to the p...

Page 41: ...B40 I 1 TEE L IU lIiI 1104BC F TO F BARREL 1250 0080 FEEDTH F TERMIN Figure 2 8 DV Single Channel Phase Accuracy Test Setup Procedure BNC CABLE 8120 1838 1250 0781 50 OHM ROUGH ATION A Connect the test instruments as shown in figure 2 8 Refer to Initial EquipmentSetup section 2 6 for unspecified parameters B Set the test instruments initially as follows Frequency Synthesizer Frequency Amplitude DC...

Page 42: ...N DOW UNIFRM SHECT TRIG O V EXT MEAS DISP FILTRD INPUT AVRG LINEAR SPEC 1 B LINEAR SPEC 2 A B COORD PHASE START X 9 kHz D Record the Ya marker reading on the Operational Verification Test Record for CHAN 1 E Record the Yb marker reading on the Operational Verification Test Record for CHAN 2 F Set the frequency Synthesizer as follows Frequency 99 kHz 2 20 ...

Page 43: ...g Section VI I None A33 A35 Input Boards A32 A34 Analog Digital Converter Boards A31 Trigger Board A6 Digital Filter Controller A1 Digital Source 2 1 4 NOISE AND SPURIOUS SIGNAL LEVEL This test measures the level of the noise floor and any spurious signals generated within the HP 3562A Required Test Equipment 2 son feedthrough terminations H P 11048C 11 I 000 8 DDD gJ DDD ODD DD 0 0 ODD DD M WW J ...

Page 44: ...ws PRESET CAl RANGE INPUT CO UPLE FREQ AVG WIN DOW U N ITS C Perform steps 1 through 4 RESET SINGLE CAL 51 dBVrms CHAN 1 AC CHAN 2 AC FREQ SPAN START FREQ 20 STABLE UNI FRM P SPEC UNITS 1 Press the HP 3562A keys as follows START SCALE SPCl MARKER Y AUTO SCALE MRKR PEAK 1 kHz 20 Hz ENTER VOLTS RMS VOLTS 2 If the Ya marker reading is less than or equal to 131 dBVrms check PASS on the Operation Verif...

Page 45: ...als Start Frequency Frequency Span Specification 20 Hz 1 kHz 1 31 dBV 1 kHz 10 kHz 1 31 dBV 90 kHz 10 kHz 1 31 dBV D For the rest of the start frequencies in table 2 3 perform steps 1 through 4 1 Press the HP 3562A keys as follows FREQ A START SPCL MARKER START FREQ FREQ SPAN MRKR PEAK To start frequency in table To frequency span in table 2 If the Ya marker reading is less than or equal to 1 31 d...

Page 46: ...cy Span Specification 20 Hz 1 kHz 5 1 34 dBV JRZ 1 kHz 50 kHz 5 144 dBV JRZ 50 kHz 50 kHz 5 144 dBV JRZ E Press the HP 3562A keys as follows WIN DOW U N ITS FLAT TOP P SPEC UNITS V JHZ F For each of the start frequencies listed in table 2 4 perform steps 1 through 5 1 Press the HP 3562A keys as follows FREQ START FREQ FREQ SPAN START To start frequency in table To frequency span in table 2 When th...

Page 47: ...ord for CHAN 2 If Test Fails Check Adjustments Section I I I Troubleshooting Section VII 2nd Pass Gain Adjustment ADC Offset and Reference Adjustment A33 A35 Input Boards A32 A34 Analog Digital Converter AS Digital Filter A4 Local Oscillator 2 1 5 SOURCE AMPLITUDE ACCURACY AND FLATNESS This test measures the amplitude accuracy and flatness of the H P 3562A source Requi red Test Equipment None Proc...

Page 48: ... and the 11 dB limits check PASS on the Operation Verification Test Record for the 0 to 65 kHz span D Press the HP 3562A keys as follows FREQ START START FREQ E When the sweep is complete perform stage 1 and 2 1 Press the HP 3562A keys as follows SCALE Y FIXD SCALE 65 kHz 8 5 1 1 dB 2 If the trace is between the 8 5 dB and the 1 1 dB limits check PASS on the Opera tion Verification Test Record for...

Page 49: ...racy and flatness CHAN 1 and CHAN 2 Floating Specification Lower Limit Upper Limit 8 849 dBV 9 1 51 dBV 8 849 dBV 9 1 51 dBV 0 1 51 3 dBV 0 1 51 3 dBV 0 1 51 3 dBV 0 1 51 3 dBV 1 3 1 5 dBV 1 2 85 dBV 1 3 1 5 dBV 1 2 85 dBV 2 10 Amplitude and Phase Match PASS Ampl itude Part Specification 0 1 dB 4 0 1 dB 5 0 1 dB 6 2 11 frequency Accuracy Specification Lower Limit Upper Limit 98 996 kHz 99 004 kHz ...

Page 50: ...acy Signal Frequency Trigger Specification Measured Value Slope Type Lower Limit Upper Limit CHAN 1 CHAN 2 9 kHz pas EXT 92 5 87 5 99 kHz pas CHAN 1 102 78 0 2 14 Noise and Spurious Signal Level Spurious Signals Start Frequency PASS PASS Specification Frequency Span CHAN 1 CHAN 2 20 Hz 1 kHz 0 1 31 dBV 1 kHz 10 kHz 0 1 31 dBV 90 kHz 10 kHz 0 1 31 dBV Noise Level Start Frequency PASS PASS Specifica...

Page 51: ...keys In this section the hard keys are in bold text and the soft keys are in regular test For example FREQ FREQ SPAN 10 kHz This example instructs you to press the hard key FREQ and the soft key FREQ SPAN After pressing the soft key FREQ SPAN enter 10 kHz 3 Refer to figure 2 10 for the position of the X and Y marker readings 4 Record the results of each of the performance tests on the Performance ...

Page 52: ...pment of table 1 4 is used to complete the performance tests the instruments listed below must be setto the preset conditions listed before begin ning the test In each test any unspecified parameters should be set to the following con ditions HP 3325A Frequency Synthesizer Function Frequency Amplitude Phase dc Offset Modulation Sweep Fluke 5200 AC Calibrator Frequency Amplitude Voltage Error Verni...

Page 53: ... SPCL FCTN SELF TEST 2 This test takes about 0 5 minutes to complete 3 When SELF TEST PASSES is displayed in the lower right corner of the display check PASS on the Performance Test Record If Test Fails Go to Fault Isolation Section VII 2 2 2 DC OFFSET This test measures the level of the dc offset generated within the HP 3562A with auto on Specification For range settings between 27 dBV and 35 dBV...

Page 54: ...ng 7 dBVrms 35 dBVrms 51 dBVrms Specification 23 dBV 65 dBV 71 dBV 11 II 000 8 DDD gJ 000 DDD 000 000 ODD DD 000 8 ODD DD M WW J 000 FEEDTHROUGH TER N g 11 ALLI G ATOR CLIP CABLES Figure 2 1 1 DC Offset Test Setup Procedure A Connect the test instruments as shown in figure 2 1 1 Keep the leads to chassis ground as short as possible ...

Page 55: ...gh 3 1 Press the HP 3562A keys as follows RANGE START To range setting in table 2 Record thE Ya marker reading on the performance test record for the CHAN 1 measured value 3 Record the Yb marker reading on the performance test record for the CHAN 2 measured value If Test Fails Check Adjustments Section I I I Troubleshooting Section VI I Track and Hold Offset Adjustment Input DC Offset Adjustment A...

Page 56: ...ill not deviate from the actual signal amplitude by more than Range Setting 27 dBV to 40 dBV 41 dBV to 51 dBV Accuracy 0 1 5 dB 0 01 5 Range Setting 0 25 dB 0 025 Range Setting If the measurement of a signal includes a signal between the BNC shel l and the chassis the marker amplitude reading will not deviate from the actual signal amplitude by more than Range Setting 27 dBV to 40 dBV 41 dBV to 51...

Page 57: ...A F TO 1 1 00 1 60 0 0 1 1250 8NC CABLE 8 1 20 1 838 1250 078 1 F BARREL 0080 BANANA BANANA L __J Figure 2 1 2 Amplitude Accuracy and Flatness Test Setup Procedure A Connect the test instruments as shown in figure 2 12 Refer to Initial EquipmentSetup paragraph 2 20 for unspecified parameters B Set the test instruments initially as follows Frequency Synthesizer Amplitude Frequency Function AC Calib...

Page 58: ...87 Vrms 1 3 dBVrms 90 kHz 22387 Vrms 1 3 dBVrms 99 kHz 22387 Vrms 23 dBVrms 1 kHz 70 795 mVrms 23 dBVrms 99 kHz 70 795 mVrms 26 dBVrms 1 kHz 50 119 mVrms 21 dBVrms 1 kHz 89 1 25 mVrms 1 7 dBVrms 1 kHz 141 25 Vrms 1 4 dBVrms 1 kHz 1 9953 Vrms 1 1 dBVrms 1 kHz 281 84 Vrms 2 36 ENTER VOLTS RMS VOLTS MODEL 3562 Specification Lower Limit Upper Limit 8 849 dBV 9 1 51 dBV 8 849 dBV 9 1 51 dBV 1 3 1 5 dBV...

Page 59: ... measured value CHAN 1 7 Record the Yb marker reading on the Performance Test Record for the measured value CHAN 2 Table 2 7 Amplitude Accuracy and Flatness Measurement Two BNC shell grounded HP 3562A Range Signal AC Calibrator Setting Frequency Amplitude 51 dBVrms 1 kHz 2 8184 mVrms 49 dBVrms 1 kHz 3 5481 mVrms 47 dBVrms 1 kHz 4 4668 mVrms 45 dBVrms 1 kHz 5 6234 mVrms 43 dBVrms 1 kHz 7 0795 mVrms...

Page 60: ...Vrms 7 499 dBV 11 dBVrms 1 kHz 27701 Vrms 11 50 dBV 1 3 dBVrms 1 kHz 21404 Vrms 13 50 dBV 1 3 dBVrms 50 kHz 21404 Vrms 1 3 50 dBV 1 3 dBVrms 90 kHz 21404 Vrms 1 3 50 dBV 1 3 dBVrms 99 kHz 21404 Vrms 1 3 50 dBV 27 dBVrms 1 kHz 43 702 mVrms 27 50 dBV 27 dBVrms 99 kHz 43 702 mVrms 27 50 dBV H Repeat part D using table 2 8 for measurement three If Test Fails Check Adjustments Section I I I Troubleshoo...

Page 61: ... the measurement of a signal includes a signal between the BNC shell and the chassis the marker amplitude reading will not deviate from the actual signal amplitude by more than Range Setting 27 dBV to 40 dBV 41 dBV to 51 dBV Required Test Equipment Frequency Synthesizer AC Calibrator BNC Procedure Accuracy 0 50 dB 01 5 Range Setting 0 60 dB 025 Range Setting HP 3325A Fluke 5200A HP 1250 0781 A Con...

Page 62: ...ollows PRESET RESET CAl SINGLE CAL WINDOW FLAT TOP AVG 4 STABLE RANGE 21 dBVrms FREQUENCY SYNTHESIZER HP 3325A I 1 c J 8 m IDDDD11 10000 1 00 88 ggggg w w o 8 00000 0 BNC CABLE 8 1 20 1 B40 HP 3562A 11 II lrnooo gJ ODD o 8 G ggg l J WW MODE L 3562 1 c k7 BNC CABLE 8 1 20 1838 BNC OUAL BANANA 1 10 0 1 60001 BANANA BANANA ENTER I T F 1 EE 1250 0781 TO F BARREL 250 00BO FREQ CENTER FREQ 10 kHz 2 40 ...

Page 63: ...rms 942 6 mVrms 100 0 mVrms 103 2 mVrms 96 79 mVrms 1 07 4 mVrms 92 91 mVrms 10 00 mVrms 11 67 mVrms 8 329 mVrms 1 2 09 mVrms 7 941 mVrms 3 1 623 mVrms 4 71 7 mVrms 1 608 mVrms 4 850 mVrms 1 485 mVrms 1 000 mVrms 2 51 7 mVrms 51 7 1 uVrms 2 559 mVrms 555 9 uVrms D For each of the amplitudes listed in table 2 9 perform steps 1 through 4 1 Set the ac calibrator s amplitude 2 Press the HP 3562A keys ...

Page 64: ...t Flatness Adjustment Input Attenuator Adjustments Calibrator Adjustment A33 A35 Input Boards A32 A34 Analog Digital Converter Boards A30 Analog Source Board 2 2 5 AMPLITUDE AND PHASE MATCH This test determines if the HP 3562A s amplitude and phase match between channel 1 and channel 2 are within the specified limits Specification BNC shell of both channels grounded The amplitude deviation between...

Page 65: ...C DUAL BANANA 1 1 0 0 1 60 0 0 1 Figure 2 1 4 Amplitude and Phase Match Test Setup Procedure A Connect the HP 3562A as shown in figure 2 14 The cables to channel 1 and channel 2 must be the same length B Press the HP 3562A keys as follows PRESET RESET CAL SINGLE CAL INPUT COUPLE CHAN1 AC CHAN2 AC GROUND CHAN1 GROUND CHAN2 SE LECT TRIG O V SOURCE TRIG 2 43 ...

Page 66: ... SOURCE SCALE START y 47 dBVrms SOURCE LEVEL Y FIXD SCALE 1 1 dB ENTER 375 1 00 kHz 49 dBVrms 2 2 dB 2 If the measurement is within the marker band check PASS on the Performance Test Record for part 1 3 Press the HP 3562A keys as follows RANGE o dBVrms SOURCE SOURCE LEVEL START y 1 1 dB o dBVrms 4 If the measurement is within the marker band check PASS on the Performance Test Record for part 2 ...

Page 67: ...ss the H P 3562A keys as fol lows RANGE SOU RCE COORD START SCA LE y 47 dBVrms SOURCE LEVEL PHASE Y FIXD SCALE Y VALUE 49 dBVrms 1 1 Degree 5 5 Degree 2 If the measurement is within the marker band check PASS on the Performance Test Record for part 4 3 Press the HP 3562A keys as follows RANGE o dBVrms SOU RCE SOURCE LEVEL START y Y VALUE o dBVrms 5 5 Degree 4 If the measurement is within the marke...

Page 68: ...tors so the center conductor of each chan nel s BNC is grounded F Perform steps 1 through 4 1 Press the H P 3562A keys as follows I N PUT COUPLE COORD SCALE RANGE SOU RCE START y FLOAT CHAN1 FLOAT CHAN2 MAC dB Y FIXD SCALE 1 3 dBVrms SOURCE LEVEL Y VALUE 1 1 dB 1 3 dBVrms 8 8 dB 2 If the measurement is within the marker band check PASS on the Performance Test Record for part 7 3 Press the HP 3562A...

Page 69: ...d check PASS on the Performance Test Record for part 9 3 Press the HP 3562A keys as follows RANGE 8 dBVrms SOURCE SOURCE LEVEL 8 dBVrms START y Y VALUE 8 5 8 5 Degree 4 If the measurement is within the marker band check PASS on the Performance Test Record for part 10 If Test Fails Check Adjustments Section I I I Troubleshooting Section VI I 2nd Pass Gain Adjustment ADC Offset and Reference Adjustm...

Page 70: ...uencies other than those listed in the table when performing th is test Specification All signals aliasing into the 0 to 100 kHz frequency span will be attenuated at least 80 dB below the range setting Required Test Equipment Frequency Synthesizer son feedthrough termination BNC Tee FREQUENCY SYNTHESIZER HP 3325A I I D 8 10 0 011881 DDDDD II 110 0 0 0 01 0 0 0 88 ggggg lU1 o 8 00000 0 ill BNC BNC ...

Page 71: ...unspecified parameters B Set the test instruments initially as follows Frequency Synthesizer Amplitude Frequency Function 1 Vrms 1 56 kHz Sine Wave C Press the HP 3562A keys as follows PRESET CAL RANGE AVG WINDOW I N PUT CO UPLE A B U N ITS RESET SINGLE CAL 1 Vrms 1 6 STABLE FLAT TOP GROUND CHAN1 GROUND CHAN2 P SPEC UN ITS ENTER VOLTS RMS VOLTS 2 49 ...

Page 72: ...g is less than or equal to 80 dBVrms check PASS on the Perfor mance Test Record for CHAN 1 4 If the Yb reading is less than or equal to 80 dBVrms check PASS on the Perfor mance Test Record for CHAN 2 If Test Fails Check Adjustments Section I I I Troubleshooting Section VI I I None A32 A34 Analog Digital Converter Boards 2 2 7 FREQUENCY ACCURACY This test measures the frequency accuracy of the HP 3...

Page 73: ...equency Accuracy Test Setup Procedure A Connect the test equipment as shown in figure 2 16 Refer to Initial Equipment Setup paragraph 2 20 for unspecified parameters B Set the test instruments initially as follows Frequency Synthesizer Frequency Amplitude Function 99 kHz 1 Vrms Sine Wave C Press the HP 3562A keys as follows PRESET CAL RANGE FREQ AVG START x RESET SINGLE CAL o dBVrms CENTER FREQ FR...

Page 74: ...pled modes The insertion loss is calculated as dc Coupled Amplitude ac Coupled Amplitude Specification Insertion Loss The insertion loss at 1 Hz due to the ac coupling capacitors will be less than 3 dB 41 3 Required Test Equipment Frequency Synthesizer son feedthrough termination BNC Tee FREQUENCY SYNTHESIZER HP 3325A I 1 0 8 m IDDDD I 1000001 00 88 ggggg m m o 8 00000 0 ill 8NC 8NC 8120 1840 H P ...

Page 75: ...Frequency Synthesizer Frequency Amplitude Function 1 Hz 1 Vrms Sine Wave C Press the HP 3562A keys as follows PRESET CAL RANGE FREQ WIN DOW AVG U N ITS I N PUT COU PLE START x SAVE RECALL I N PUT COUPLE START MATH RESET SINGLE CAL 1 Vrms FREQ SPAN UNI FRM 4 STABLE P SPEC UNITS CHAN1 AC 1 Hz SAVE DATA CHAN1 DC DIV NOTE Ignore math overflow message 1 00 Hz ENTER VOLTS RMS VOLTS X MRKR SCALE 1 SAVED ...

Page 76: ...e Troubleshooting Section VI I I A33 A35 Input Boards 2 29 SINGLE CHANNEL PHASE ACCURACY This test measures the phase accuracy of the HP 3562A relative to the phase of the trig ger signal The frequency synthesizer is used to input a square wave to one channel and the external trigger input Specification When the BNC shell of a channel is grounded the marker phase reading will not deviate from the ...

Page 77: ... degrees HP 3325A HP 11048C HP 1250 0781 HP 3562A 0If Gl QQD_ DD DD o 8 000 u o ODD BB G ggg M r o 0 000 000 l L BNC BNC 1 8 1 20 1 838 TEE F T 125 BNC CABLE 8 120 1 838 1 250 078 1 o F BARREL 0 0080 50 OHM FEEOTHROUGH TERMINATION H P 1 1 048C lBNC DUAL BANANA 5 1 2297 TEE 1 250 078 J HP 1 2 tBNC Fl BANANA MALE PDMONA MODEL 1 296 Figure 2 1 B Single Channel Phase Accuracy Test Setup Procedure A Co...

Page 78: ...62A keys as follows PRESET RESET CAl SINGLE CAL SHECT MEAS POWER SPEC INPUT COUPLE GROUND CHAN1 G ROUND CHAN2 AVG 5 ENTER STABLE TIM AV ON WINDOW UNIFRM SHECT TRIG O V MEAS DISP FILTRD INPUT AVRG LINEAR SPEC 1 B LINEAR SPEC 2 A B COORD PHASE 2 56 ...

Page 79: ...4 1 Set the frequency Synthesizer as follows Frequency To signal frequency in table 2 Press the HP 3562A keys as follows SE LECT TRIG START x To trigger slope in table To trigger type in table To signal frequency in table 3 Record the Ya marker reading on the Performance Test Record for CHAN 1 measured value BNC shell grounded 4 Record the Yb marker reading on the Performance Test Record for CHAN ...

Page 80: ...dance of the HP 3562A as a series resistance and capacitance The digital multimeter is used to measure the input resistance directly The input capacitance is then measured by inputting a 100 kHz signal from the frequency synthesizer This equation is used to calculate the capacitance C 1 S 9 pF 159 pF Note An LCR meter HP 4261 A HP 4332A can be used to measure the input capacitance directly Specifi...

Page 81: ...1 1 00 1 6000 1 Gl Q QO_ OOO dd 8D8 Oo gJ o OOO o BB Q ggg gg J Jr I A Connect the test instruments as shown in figure 2 19 Refer to Initial Equipment Setup paragraph 2 20 for unspecified parameters B Set the digital voltmeter initially as follows C Function Range Trigger 2 WIRE OHM AUTO INTERNAL Press the HP 3562A keys as follows PRESET RESET CAL SINGLE CAL I N PUT COU P LE GROUND CHAN 1 GROUND C...

Page 82: ...r reading on the Performance Test Record E Change the BNC input connector to channel 2 and repeat part D H P 3562A FREQUENCY SYNTHESIZER 11 II HP 3325A mJ OOcru I I IJ CD o oG i 10 0 0 1188 W DDDD o 0 0 88 88888 o CD 00000 1 110 0 0 0 1 0 tIl M WW J 100k 1 SERIES RESISTOR SEE FIGURE 1 4 50 r t BNC BNC 8120 1840 Figure 2 20 Input Capacitance Test Setup F Connect the test instruments as shown in fig...

Page 83: ...E CHAN 1 AC CHAN 2 AC GROUND CHAN 1 GROUND CHAN 2 o dBVrms P SPEC UNITS MAG LlN 100 kHz ENTER VOLTS RMS VOLTS I Record the Ya amplitude reading in the Vc position of the Performance Test Record for CHAN 1 J Perform steps 1 through 3 1 Connect the son feedthrough to channel 2 2 Press the HP 3S62A keys as follows B START COORD MAG LlN 2 61 ...

Page 84: ...H P 3S62A keys as follows A START 2 Record the Ya amplitude reading in the Vin position of the Performance Test Record for CHAN 1 M Perform steps 1 through 3 1 Connect the son feedthrough to channel 2 2 Press the HP 3S62A keys as follows B START 3 Record the Yb amplitude reading in the Vin position of the Perf rmance Test Record for CHAN 2 N Use the equation given on the Performance Test Record to...

Page 85: ...lator 6000 feedthrough termination SI GNAL ANALYZER HP 339A I g o 0 0 HP 339A HP 11095A HP 3562A l Ui fill 7BNC CABLE B 1 20 1 B38 oo L _ _ B A N c AN c A BA c N A c NA _ _ _ _ _ TEE 1 250 07 8 1 H P 1 1 04BC F TO F BARREL TO J TO 50 OHM 1 250 00BO H R6 TAB A A BNC DUAL BANANA FEEDTHROUGH TERMINATI ON GROUND 1 100 1 6000 1 Figure 2 2 1 Harmonic Distortion Test Setup 1 Procedure A Connect the test ...

Page 86: ... SIGNAL Frequency FREQU ENCY 49 kHz 49500 Hz 32 kHz 33000 Hz 24 kHz 24750 Hz 19 kHz 1 9800 Hz RESET SINGLE CAL o dBVrms CHAN 1 AC CHAN 2 AC GROUND CHAN 1 GROUND CHAN 2 FLAT TOP P SPEC UN ITS Harmonic Number 2nd 3rd 4th 5th VOLTS RMS VOLTS Harmonic Frequency 99 kHz 99 kHz 99 kHz 99 kHz D For each of the signal frequencies listed in table 2 1 3 perform steps 1 through 7 1 Set the low distortion osci...

Page 87: ... the signal frequency 4 Adjust the low distortion oscillator s amplitude vernier until Ya O dBVrms O 1 dBVrms 5 Press the HP 3562A keys as follows A B AVG 4 STABLE FREQ MAX SPAN START x 99 kHz ENTER 6 Record the Ya marker amplitude reading on the Performance Test Record as the harmonic frequency amplitude for channel 1 7 Record the Yb marker amplitude reading on the Performance Test Record as the ...

Page 88: ...EE 1 250 07B 1 F TO F BARREL 1250 00BO E For measurement two connect the test instruments as shown in figure 2 22 The chassis ground cable must go to the ground terminal of the low distortion oscillator F Press the HP 3562A keys as follows INPUT COU PLE FLOAT CHAN 1 FLOAT CHAN 2 C Repeat part D for measurement two If Test Fails Check Adjustments Section I I I Troubleshooting Section VII 2nd Pass C...

Page 89: ...esizers 2 50n feedthrough terminations 2 1 kn resistors 2 BNC Tee FREQUENCY SYNTHESI ZER HP 3325A I 1 0 8 m looooil 1888881 88 88 ggggg o 8 00000 8 ill BNC BNC 8 1 20 1 840 FREQUENCY SYNTHESIZER HP 3325A I 1 0 8 1888118811OOOOi11 11888881 88 88 ggggg o 8 00000 8 ill BNC BNC B 1 20 1 B40 HP 3325A HP 11048C HP 0757 0465 HP 1250 0781 HP 3562A D M o 0 000 000 QQO_ ooo oo 000 8 oo gJ 00 BOO ooo BBBG gg...

Page 90: ...e test instruments initially as follows Frequency Synthesizer 1 Frequency Amplitude Function Frequency Synthesizer 2 Frequency Amplitude Function C Perform steps 1 through 5 20 kHz 1 Vrms Sine Wave 26 kHz 1 Vrms Sine Wave 1 Press the HP 3562A keys as follows PRESET CAL RANGE INPUT COUPLE WINDOW FREQ U N ITS A B x RESET SI NG LE CAL 2 Vrms GROUND CHAN 1 GROUND CHAN 2 FLAT TOP CENTER FREQ P SPEC UNI...

Page 91: ...kHz 20 kHz 26 kHz 14 kHz 20 kHz 26 kHz 12 kHz 20 kHz 26 kHz 8 kHz ENTER 1 00 1 dB D For each of the harmonic frequencies listed in table 2 14 perform steps 1 through 3 1 Press the H P 3562A keys as follows FREQ CENTER FREQ START To harmonic frequency in table x To harmonic frequency in table 2 If the Ya marker reading is less than or equal to 80 dBVrms check PASS on the Performance Test Record for...

Page 92: ... C IFI DU L B l C TE FREQUENCY SYNTHESI ZER HP 3325A NC BANANA P 125 1 2277 I I c J c J 1K OHM SERIES __ 1 rT A B Immml1881 00000 1 llmmmmml RESI STOR mmm 88 BBBBB IHl HP o c J 00000 t m ill SEE F I G 0 1 1 0 48C 1 4 I Pd 50 0HM 0 BNC 8NC 8 1 20 1840 FEEDTHROUGH TERMI NATION Figure 2 24 Intermodulation Distortion Test Setup 2 E Perform steps 1 and 2 T A B 1 Connect the test instruments as shown in...

Page 93: ...ded 3 If the Yb marker reading is less than or equal to 80 dBVrms check PASS on the Performance Test Record for measurement one channel 2 with the BNC center conductor grounded G Connect the test instruments as shown in figure 2 23 H Set the test instruments as follows Frequency Synthesizer 1 Frequency 89 kHz Frequency Synthesizer 2 Frequency I Perform steps 1 through 5 99 kHz 1 Press the HP 3562A...

Page 94: ...c frequency in table x To harmonic frequency in table 2 If the Ya marker reading is less than or equal to 80 dBVrms check PASS on the Performance Test Record for measurement two channel 1 with the BNC shell floating 3 If the Yb marker reading is less than or equal to 80 dBVrms check PASS on the Performance Test Record for measurement two channel 2 with the BNC shell floating K Connect the test ins...

Page 95: ...alog Digital Converter Boards 2 3 3 NOISE AND SPURIOUS SIGNAL LEVEL This test measures the level of the noise floor and any spurious signals generated within the HP 3S62A Specification When the input is terminated with a son load the amplitude of all spurious signals must be at least 80 dB below the range setting When using a flat top window and a son load the average noise level must be less than...

Page 96: ...ows PRESET CAL RANGE I N PUT COUPLE FREQ AVG WINDOW U N ITS RESET SINGLE CAL 51 dBVrms CHAN 1 AC CHAN 2 AC FREQ SPAN START FREQ 20 STABLE UNIFRM P SPEC UN ITS C Perform steps 1 through 4 1 Press the H P 3562A keys as follows START SCALE SPC L MARKER Y AUTO SCALE MRKR PEAK 1 kHz 20 Hz ENTER VOLTS RMS VOLTS 2 If the Ya marker reading is less than or equal to 131 dBVrms check PASS on the Performance ...

Page 97: ...n Specification 20 Hz 1 kHz 5 131 dBV 1 kHz 10 kHz 5 1 31 dBV 10 kHz 10 kHz 5 1 31 dBV 20 kHz 10 kHz 5 131 dBV 30 kHz 10 kHz 5 131 dBV 40 kHz 10 kHz 5 1 31 dBV 50 kHz 10 kHz 5 131 dBV 60 kHz 10 kHz 5 1 31 dBV 70 kHz 10 kHz 5 1 31 dBV 80 kHz 10 kHz 5 1 31 dBV 90 kHz 10 kHz 5 1 31 dBV D For the rest of the start frequencies in table 2 16 perform steps 1 through 4 1 Press the H P 3562A keys as follow...

Page 98: ... dBVrms check PASS on the Performance Test Record for CHAN 2 Table 2 1 7 Noise Level Start Frequency Frequency Span 20 Hz 1 kHz 1 kHz 50 kHz 50 kHz 50 kHz E Press the HP 3562A keys as follows Specification 1 34 dBV J HZ 144 dBV JHZ 1 44 dBV J Hz WI N DOW FLAT TOP U N ITS P SPEC UN ITS V JHz F For each of the start frequencies listed in table 2 17 perform steps 1 through 5 1 Press the H P 3562A key...

Page 99: ...oubleshooting Section VI I 2 34 CROSS TALK 2nd Pass Gain Adjustment ADC Offset and Reference Adjustment A33 A35 Input Boards A32 A34 Analog Digital Converter AS Digital Filter A4 Local Oscillator The cross talk test measures the amount of energy in one channel that has been coupled across from the other channel This is accomplished by placing a high signal level on one channel and then measuring t...

Page 100: ...EDTHROUGH TERMINATION ALLI GATOR ALLI GATOR A Connect the test instruments as shown in figure 2 26 Refer to Initial Equipment Setup paragraph 2 20 for unspecified parameters B Set the frequency synthesizer as follows Amplitude High Voltage Output Frequency Function 14 Vrms ON 100 kHz Sine Wave C Press the HP 3562A keys as follows PRESET CAl FREQ WIN DOW AVG RANGE START A B x RESET SINGLE CAL CENTE...

Page 101: ...88 o 0 1 0 0 DODO 11 110 0 0 0 0 1 ggggg 00000 0 1i BNC BNC B 1 20 1 B40 Figure 2 27 Cross Talk Channel 2 Test Setup HP 3562A 0 M o 0 000 000 Gl QQO OOO dd 000 8 Oo gJ 000 ooo 00 BB G ggg gg J J 0 H 5 T ALLI GATOR ALL I GATOR P 1 10 4BC o OHM FEEDTHROUGH ERMINAT I ON F If the delta Y is greater than or equal to 140 dB check PASS on the Performance Test Record for channel 1 G Connect the test instr...

Page 102: ...est measures the capability of the 3562A to ignore a signal which appears simultaneously and in phase at the high and low input of a single channel Specification When a common mode signal is input to a single channel the relative value compared to the amplitude of the input single will be Frequency o Hz to 66 Hz 66 Hz to 500 Hz Requ ired Test Equipment Frequency Synthesizer Common Mode Cable Proce...

Page 103: ...ection Test Setup 1 C Press the HP 3562A keys as follows PRESET RESET CAL SINGLE CAL AVG 1 6 ENTER STABLE WIN DOW FLAT TOP A B UN ITS P SPEC VOLTS UN ITS RMS VOLTS Table 2 1 8 Common Mode Rejection Signal Signal Range Range Specification Amplitude Frequency Setting 1 Setting 2 5 680 Vrms 66 Hz 16 dBVrms 8 dBVrms s 80 dB 3 41 3 Vrms 500 Hz 11 dBVrms 1 2 dBVrms s 65 dB D For each of the frequencies ...

Page 104: ...erformance Test Record as the first measurement for CHAN 2 5 Connect the test instruments as shown in figure 2 29 6 Press the HP 3562A keys as follows RANGE To range setting 2 in table START SCALE Y AUTO SCALE x To signal frequency in table HP 3562A D FREQUENCY SYNTHESIZER HP 3325A I 1 c J 0 IDDDDDll 1000001 M 00 88 88888 m o 0 00000 0 ill o 0 000 000 Gl mnr Q wwr J L I BNC BNC J TEE B 1 2 0 1B40 ...

Page 105: ...tion I I I Input dc Offset Adjustment Calibrator Adjustment Troubleshooting Section VI I A33 A35 Input Boards A30 Analog Source 2 36 EXTERNAL REFERENCE TEST This test determines if the external reference input will lock on to an external signal that is within the specified range Specification The HP 3562A will lock to external signals f 1 2 5 and 10 MHz 0 01 The amplitude of the signal must be bet...

Page 106: ...owly decrease the frequency in 100 Hz steps until the Source Not Locked message is displayed 3 Record the frequency value on the Performance Test Record E Set the Frequency Synthesizer as follows Frequency F Perform steps 1 through 4 10 000 MHz 1 Press IIPRESET on the H P 3562A 2 Press FREQ on the 3325A 3 Using the modify arros on the 3325A slowly increase the frequency in 1 kHz steps until the So...

Page 107: ...ER G i HP 3456A I I 0 0 0 0 0 0 0 0 M 0 0 0 0 0 o 0 0 t a I r 1W J 0 0 0 0 0 0 0 0 0 0 0 o 0 000 000 0 0 0 0 0 0 0 0 0 0 0 BNC OUAL BANANA 1 100 1 600 0 1 Figure 2 3 1 Source Residual Offset Test Setup Procedure A Connect the test instruments as shown in figure 2 31 Refer to Initial Equipment Setup paragraph 2 20 for unspecified parameters B Set the digital voltmeter as follows Function Trigger Ra...

Page 108: ...OURCE AMPLITUDE ACCURACY AND FLATNESS This test measures the amplitude accuracy and flatness of the HP 3562A source Specification The amplitude reading will not deviate from the source amplitude setting by more than 1 dB 1 2 2 when terminated into 1 MD for frequencies between 0 Hz and 65 kHz and 1 dB 1 5 dB for frequencies between 65 kHz and 100 kHL Procedure A Connect the HP 3562A source to chann...

Page 109: ...n the sweep is complete perform steps 1 and 2 1 Press the HP 3562A keys as follows SCALE Y FIXD SCALE 8 5 1 1 dB 2 If the trace is between the 8 5 dB and the 1 1 dB limits check PASS on the Performance Test Record for the 65 kHz to 100 kHz span If Test Fails Check Troubleshooting Section VI I I A30 Analog Source Board 2 39 SOURCE OUTPUT RESISTANCE CHARACTERIZATION Optional This test measures the o...

Page 110: ...Resistance Test Setup Procedu re A B Connect the test instruments as shown in figure 2 32 Press the HP 3562A keys as follows PRESET CAL INPUT COU PLE MEAS MODE SOU RCE START COORD U N ITS SCALE RESET SING LE CAL GROUND CHAN 1 SWEPT SINE SOURCE LEVEL MAG LI N SWEPT UNITS Y AUTO SCALE CHAN 1 AC LINEAR SWEEP 1 Vrms VOLTS MODEL 35q2 ...

Page 111: ... 1 DIV SAVED 1 MPY 50 0 2 40 SOURCE DISTORTION This test measures the level of any spurious signals generated by the HP 3562A source Specification When the source is set between dc and 10 kHz the distortion will be at least 60 dB below the signal level When the source is set between 10 kHz and 100 kHz the distortion will be at least 40 dB below the signal level Requ ired Test Equipment None Proced...

Page 112: ... Delta Y Value 60 dB 60 dB 40 dB 40 dB C For each of the range settings I isted in table 2 19 perform steps 1 through 5 1 Press the H P 3562A keys as follows Y OFF RA NGE SOU RCE START SCALE SPCl MARKER Y To range setting in table SOURCE LEVEL FIXED SINE Y AUTO SCALE MRKR PEAK To source amplitude in table To source frequency in table 2 Using the marker knob move the Y marker to the center of the X...

Page 113: ...easures the in band energy of the HP 3562A noise source using the power marker function of the HP 3562A and a true rms voltmeter Specification The percentage in band energy of the random noise will be at least 70 The percentage in band energy of the chirp will be at least 85 Required Test Equipment Digital Voltmeter BNC Tee DIGITAL VOLTMETER HP 3456A I I 0 0 0 0 0 0 0 0 0 0 0 0 0 o 0 0 0 0 0 0 0 0...

Page 114: ...the test instruments initially as follows Digital Voltmeter Function Trigger ac V V Internal C Press the HP 3562A keys as follows PRESET CAt INPUT COUPLE WIN DOW RANGE SOURCE FREQ AVG START U N ITS COORD sPCt MARKER RESET SINGLE CAL GROUND CHAN 1 U N I FRM NONE 1 Vrms SOURCE LEVEL FREQ SPAN CENTER FREQ 1 60 STABLE P SPEC U NITS MAG L1N POWER 1 Vrms 1 kHz 5 kHz ENTER VOLTS RMS VOLTS ...

Page 115: ...RECALL o 3 Record the voltmeter average on the Performance Test Record E Record the HP 3562A power measurement on the Performance Test Record F Press the HP 3562A keys as follows SOURCE SE LECT TRIG START SPCL MARKER G Repeat parts D and E PRIODC CHIRP SOURCE TRIG POWER H The percentage in band energy for random noise and chirp are calculated using the following formula HP 3562A Reading x 100 Volt...

Page 116: ...ection VI I None A30 Analog Source Board A1 Digital Source Board A4 Local Oscillator Board 2 42 PERFORMANCE TEST RECORD 2 21 Self Test 2 22 DC Offset Measured Value Range Setting CHAN 1 CHAN 2 7 dBV 35 dBV 51 dBV 2 94 MODEL 3562 PASS Specification 23 dBV 65 dBV 71 dBV ...

Page 117: ...unded Specification Measured Value Lower Limit Upper Limit CHAN 1 CHAN 2 8 849 dBV 9 1 51 dBV 8 849 dBV 9 1 51 dBV 1 3 15 dBV 1 2 85 dBV 13 1 5 dBV 1 2 85 dBV 1 3 15 dBV 1 2 85 dBV 1 3 1 5 dBV 1 2 85 dBV 23 1 5 dBV 22 85 dBV 23 1 5 dBV 22 85 dBV 26 1 5 dBV 25 85 dBV 21 1 5 dBV 20 85 dBV 1 7 1 5 dBV 1 6 85 dBV 1 4 1 5 dBV 1 3 85 dBV 11 15 dBV 1 0 85 dBV Amplitude Accuracy and Flatness Measurement T...

Page 118: ... CHAN 1 CHAN 2 7 499 dBV 8 501 dBV 7 499 dBV 8 501 dBV 11 50 dBV 10 50 dBV 1 3 50 dBV 1 2 50 dBV 1 3 50 dBV 1 2 50 dBV 1 3 50 dBV 12 50 dBV 1 3 50 dBV 1 2 50 dBV 27 50 dBV 26 50 dBV 27 50 dBV 26 50 dBV 2 24 Amplitude Linearity Signal Frequency 1 0 kHz Range Setting 10 Vrms BNC shell grounded Measured Value Specification Upper Limit Lower Limit CHAN 1 CHAN 2 10 1 8 Vrms 9 827 Vrms 1 01 9 Vrms 981 4...

Page 119: ...ication 0 1 dB 4 0 5 0 1 dB 5 0 5 0 1 dB 6 0 5 BNC center conductor grounded 0 8 dB 9 8 5 0 8 dB 10 8 8 2 26 Anti Alias Filter Response Alias PASS PASS Specification Frequency CHAN 1 CHAN 2 100 kHz 5 80 dB 72 kHz 5 80 dB 50 kHz 5 80 dB 11 kHz 5 80 dB 2 27 Frequency Accuracy Specification Measured Value Lower Limit Upper Limit 98 996 kHz 99 004 kHz 2 28 Input Coupling Insertion loss Channel 1 Chann...

Page 120: ...z pas CHAN 2 92 5 87 5 9 kHz pas EXT 92 5 87 5 9 kHz N EG EXT 87 5 92 5 99 kHz pas CHAN 1 102 78 0 99 kHz pas CHAN 2 1 02 78 0 99 kHz pas EXT 102 78 0 BNC center conductor grounded Signal Frequency Trigger Specification Measured Value 9 kHz pas CHAN 1 96 5 83 5 9 kHz pas CHAN 2 96 5 83 5 9 kHz pas EXT 96 5 83 5 9 kHz NEG EXT 83 5 96 5 99 kHz pas CHAN 1 106 74 0 99 kHz pas CHAN 2 106 74 0 99 kHz pa...

Page 121: ... 1 59 pF Measured Value Specification CHAN 1 CHAN 2 pF pF 100 pF 2 31 Harmonic Distortion Measurement One Measured Measured Channel 1 Channel 2 Signal Harmonic Harmonic Specification Frequency Frequency Frequency Amplitude Amplitude 49500 Hz 5 80 dB 33000 Hz 5 80 dB 245750 Hz 5 80 dB 1 9800 Hz 5 80 dB Measurement Two Measured Measured Channel 1 Channel 2 Signal Harmonic Harmonic Specification Freq...

Page 122: ... PASS Specification 6 kHz s 80 dB 5 80 dB 14 kHz s 80 dB s 80 dB 12 kHz s 80 dB s 80 dB 8 kHz s 80 dB s 80 dB 2 32 Intermodulation Distortion Measurement Two BNC shell floating Channel 1 Channel 2 Harmonic Frequency PASS Specification PASS Specification 1 0 kHz s 80 dB s 80 dB 79 kHz s 80 dB s 80 dB 20 kHz s 80 dB s 80 d B 69 kHz s 80 dB s 80 dB BNC center conductor grounded Channel 1 Channel 2 Ha...

Page 123: ...Hz 1 0 kHz 5 1 31 dBV 30 kHz 10 kHz 5 1 31 dBV 40 kHz 1 0 kHz 5 1 31 dBV 50 kHz 1 0 kHz 5 1 31 dBV 60 kHz 1 0 kHz 5 1 31 dBV 70 kHz 1 0 kHz 5 1 31 dBV 80 kHz 1 0 kHz 5 1 31 dBV 90 kHz 1 0 kHz 5 1 31 dBV Noise Level Start Frequency PASS PASS Specification Frequency Span CHAN 1 CHAN 2 20 Hz 1 kHz 5 1 34 dBV J HZ 1 kHz 50 kHz 5 1 44 dBV VHZ 50 kHz 50 kHz 5 1 44 dBV 2 34 Cross Talk PASS PASS Channel 1...

Page 124: ...urement CHAN 2 Second Measurement Second Measurement CHAN 1 Second Measurement CHAN 2 Relative Value Measured Value CHAN 1 Measured Value CHAN 2 2 36 External Reference Test Measured Value 2 37 Source Residual Offset Specification Lower Limit Upper Limit 10 mVpk 10 mVpk 10 mVpk 10 mVpk 2 38 Source Amplitude Accuracy and Flatness PASS PASS MODEL 3562 Specification 80 d B 65 d B Specification 80 dB ...

Page 125: ...10 kHz 25 mVpk 99 kHz 5 Vpk 99 kHz 2 41 Source Energy Measurement Random Noise HP 3562A Reading r X 100 Voltmeter Average Periodic Chirp H P 3562A Reading r X 1 00 Voltmeter Average ____ 2 70 in band energy 2 85 in band energy PERFORMANCE TESTS Specification 2 60 dB 2 60 dB 2 40 dB 2 40 dB 2 1 03 ...

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Page 127: ...7 Calibrator Gain Tables Title Adjustment Components Figures Title Power Supply Component Locator Trigger Board Component Locator Capacitive Load ADC Board Component Locator Both R408 R422 Out of Adjustment R422 Needs Adjustment R408 Needs Adjustment ADC Second Pass Gain Adjustments Complete ADC Board Component Locator Both R401 R400 Out of Adjustment R401 Adjusted to Flatten Noisy Triangle Signal...

Page 128: ......

Page 129: ...mportant when set ting the reference and calibrator The adjustments described for the ADC and input boards apply to both channel one and channel two of the analyzer front end Table 3 1 Adjustment Components Adjustment Name Board Component Power supply shut down level Pwr supply A1 8R1 20 48 MHz reference Trigger A31 R208 2nd pass offset ADC A32R408 2nd pass gain ADC A32R422 ADC offset ADC A32R400 ...

Page 130: ...e made inoperative Adjustments performed in this section are performed with power applied and the protective co vers removed These adjustments should be performed only by trained service personnel who are aware of the hazards involved such as fire and electrical shock Under no circumstances should an operator remove any covers screws sh ields or in any other wa y access the interior of the HP 3562...

Page 131: ... supply capacitors 4 Set the variable ac power supply to output 81 Vrms 2 Vrms and connect the main power cord of the HP 3562A to the variable ac power supply 5 Configure the scope for dc coupling and connect the scope input to A1 8TP1 2 using a 10 1 probe See figure 3 1 6 Turn the HP3562A on 7 Turn A1 8R1 fully CCW and then CW until the signal at TP12 goes low then turn it CCW until it just goes ...

Page 132: ...ator A1 S A22 3 5 20 48 MHz REFERENCE ADJUSTMENT Description Board Location Key This procedure adjusts the 20 48 MHz frequency reference circuit on the trigger board A31 This circuit is the source of the timing reference for the ADC boards A33 the local oscillator A4 and the main power supply A1 8 Equipment Required Frequency Standard 10 MHz Freq Standard Frequency counter HP 5351 B 1 1 scope prob...

Page 133: ...equency standard output to the counter reference input and connect the counter s main counting input to A31 TP10 VCO output using the 1 1 probe 6 Adjust A31 R208 for a counter reading of 20 48 MHz 200 Hz 7 Remove the power and return A31J201 to the normal position on the upper two pins This completes the adjustment 3 6 SECOND PASS GAIN ADJUSTMENT Description This procedure adjusts the dc offset of...

Page 134: ...ADJUSTMENTS 3 6 AZZ An AI li 9 10 Board Location Key I 20 2 30 Figure 3 2 Trigger board component locator A3 1 1 TP10 3 40 MODEL 3562 ...

Page 135: ...causes circuit failure in most cases 1 Disconnect the I ine power cord from the rear panel of the H P 3562A HP PIN 01 60 2230 1 250 0045 1 250 001 8 0360 1 632 2950 0043 2 Remove the ADC board to be adjusted and place it on the extender board 3 Reconnect the line power cord and turn the power switch ON 4 Connect A32TP400 to a ground test point with a shorting clip This disables the offset DAC 5 Re...

Page 136: ...oard component locator A32 If the circuit is badly out of adjustment the signal may appear as a triangle waveform with either the upper or lower corners extending outward as spikes as shown in figure 3 5 The following adjustments should reduce the spikes to form a regular triangle waveshape and then flatten the triangle waveform into a straight line as shown in figure 3 8 The noise remaining after...

Page 137: ...ments complete This completes the adjustment If no more adjustments are to be made to this board remove the line power cord from the HP 3562A rear panel remove the extender board and reinstall the ADC board in the card cage 3 7 ADC OFFSET AND REFERENCE ADJUSTMENT Description This procedure nulls the ADC s dc offset and optimizes its reference voltage NOTE The second pass gain adjustment described ...

Page 138: ...en PRESET RESET RANGE 7 dBVrms SPCL FCTN BEEPER ON OFF 66 ENTER Dither off if still in second pass only from previous adjustment beeper 68 enter will return to normal two pass operation NOTf Pressing the beeper key toggles the beeper between on and off It does not matter whether the beeper is turned on or off as long as the keys are pressed in the order specified If beeper commands have been activ...

Page 139: ...TP40S Figure 3 9 ADC board component locator A32 r 4 1 J I r r Figure 3 1 0 Both R401 R400 out of adjustment I j j I Figure 3 1 1 R401 adjusted to flatten noisy triangle signal Figure 3 1 2 R400 adjusted to place noisy line in the center of the triangle signal ADJ USTMENTS 3 11 ...

Page 140: ...ent 3 6 is performed for optimal dc response Equipment Required Extender board part of kit 03562 84401 HP 03562 66542 CAUTION Instrument power should always be turned off before an y boards are removed or installed Failing to do so causes circuit failure in most cases Procedure 1 Disconnect the line power cord from the rear panel of the HP 3562A 2 Remove the ADC board to be adjusted and place it o...

Page 141: ...ts wh ich do not allow accurate measurements to be made 8 Numbers appear on the screen under the headings Channel 1 and Channel 2 1 Ad just A32R408 until the number corresponding to the channel under test is 0 16 This completes the adjustment of the ADC board Remove the line power cord from the HP 3562A rear panel return jumper 1300 to the upper two pins normal position remove the shorting clip be...

Page 142: ...t the coax between the input board and its accompanying ADC board 3 Remove the ADC board of the same channel as the input board under adjustment and ground TP400 Replace the board in the instrument 4 Short all three pins of the input connector A33J300 and A33TP501 together Since the center pin of the input connector is ground this grounds the input signals and TP501 5 Reconnect the line power cord...

Page 143: ...the line power cord from the H P 3562A rear panel remove the ground wire from the ADC board remove the extender board and reinstall the input board in the card cage 3 10 INPUT ATTENUATORS Description These adjustments setthe input attenuation levels on either of the two input boards A33 or A35 There are two pair of attenuators on each channel In measurements made with reference to ground two atten...

Page 144: ...der board 3 Reconnect the line power cord and turn the power switch ON 4 Connect the front two pins of the input connector together This grounds the low side of the differential input signal 5 Press the following keys in the order given PRESET RANGE PAUSE CO NT SPCl FCTN RESET 1 dBVrms disables autoranging SERVIC TEST LOOP ON TEST INPUT FR END ADJ UST SIDE A 40 dB Numbers should appear on the scre...

Page 145: ...dB softkey 11 Adjust A33C106 for a zero reading on the H P 3562A display 12 Press the SIDE B 20 dB softkey 1 3 Adjust A33C102 for a zero reading on the H P 3562A display 0 0 ill o TP4 11 This completes the adjustment Disconnect the line power cord from the HP 3562A rear panel remove the extender board and reinstall the input board in the card cage 3 17 ...

Page 146: ...e following keys in the order given SOURCE SOURCE LEVEL DC OFFSET o Vpk 10 Vpk 3 Connectthe digital voltmeter to the HP 3562A source front panel output using a BNC cable and a BNC to banana adapter 4 Adjust A30R9 for a 10 V 75 mV reading on the voltmeter 5 Press the DC OFFSET softkey and enter a 10 Vpk offset 6 Check for a 10 V voltmeter reading Adjust A30R9 so both the the 10 V setting and the 10...

Page 147: ...I I ODEL 3562A R9 o A22 Board Location Key ILs5lL A L S J3 1 10 5 20 25 30 3 5 1 Figure 3 1 6 Analog source component locator A30R9 ADJ USTMENTS 3 19 ...

Page 148: ... phase lock ON 2 Preset the HP 3562A by pressing the PRESET hardkey and the RESET softkey 3 Set the calibrator for 0 2 Vrms and 4 kHz 4 Connect the calibrator output to the HP 3562A Input 1 5 Press the following keys in the order given PAU SE CONT SPC l FCTN SERVIC TEST LOOP ON TEST INPUT FR END ADJUST CALl BR ADJ UST 6 The HP 3562A display should now show a number that is constantly changing Adju...

Page 149: ...IODEL 3562A R1 0 A22 Board Location Key Figure 3 1 7 Analog source component locator A30R 1 0 ADJUSTMENTS 3 21 3 22 ...

Page 150: ......

Page 151: ...ACEABLE PARTS Contents Title Page Introduction 4 1 Replaceable Parts List 4 1 Ordering Information 4 2 Tables Title Reference Designations and Abbreviations Manufacturers Code List Replaceable Parts Figures Title Board and Cable Diagram Cabinet Parts Exploded View Page 4 6 4 7 4 8 4 9 Page 4 3 4 4 4 5 ...

Page 152: ......

Page 153: ...asteners for the cabinet an M designation is under the front bezel plastic trim strip 4 2 REPLACEABLE PARTS LIST Table 4 3 is organized as follows 1 PC boards and their components is alphanumeric order by reference designators 2 Chassis mounted components and hardware grouped by top bottom front back and side assemblies Cables are included in a separate group The information for each part consists...

Page 154: ... Address the order to the nearest Hewlett Packard office Direct Mail Order System Within the U 5 A Hewlett Packard can supply parts through a direct mail order system Advantages of using this system are It Direct ordering and shipment from the HP Parts Center in Mountain View California It No maximum or minimum on any mail order There is a minimum order for parts ordered through a local HP sales a...

Page 155: ...ional 5061 9679 Corner strut with tapped holes 4 5021 5838 Top cover 1 5061 9436 Bottom cover 1 5061 9448 Side cover perforated with handle recess 5060 9948 Strap handle 5060 9805 Front dress panel 1 03562 00201 Front sub panel 1 03562 00202 Rear panel 1 03562 00203 Screw 1 6 0515 1331 Screw attaches to CRT bezel 4 051 5 0889 Screw 1 051 5 0081 Lock washer 1 21 90 0047 Screw 4 0515 1 1 32 Screw 5 ...

Page 156: ... V vacw var vdcw W wl wiv w o Designators assembly motor battery capacitor diode or thyristor delay line Iamp mise electronic part fuse Iilter heater integrated circuit jack relay inductor meter mechanical part plug Q QCR R p RT S T TB TC TP TS U V w X XDS XF Y z negative positive zero zero temperature coefficient nanosecond s 10 9 seconds not separately replaceable ohm s order by description outs...

Page 157: ...andle optional 2 5061 9679 5061 0079 15 Corner strut with tapped holes 4 5021 5838 5020 8838 1 6 510 Top cover 1 5061 9436 5060 9836 1 7 511 Bottom cover 1 5061 9448 5060 9848 1 8 Side cover perforated with handle recess 2 5060 9948 1 9 509 Strap handle 2 5060 9805 20 100 Front dress panel 1 03562 00201 21 101 Front sub panel 1 03562 00202 22 200 Rear panel 1 03562 00203 23 Screw 1 6 051 5 1 331 2...

Page 158: ...TSTR V vacw var vdcw W wl wiv w o Designators assembly motor battery capacitor diode or thyristor delay line Iamp mise electronic part fuse filter heater integrated circuit jack relay inductor meter mechanical part plug Q QCR R p RT S T TB Te TP TS U V W X XDS XF Y Z negative positive zero zero temperature coefficient nanosecond s 10 9 seconds not separately replaceable ohm s order by description ...

Page 159: ...mington Wilmington Molex Inc Lisle Tharco Precision Inc San Lorenzo Hewlett Paekard Co Corporate HQ Palo Alto Isotemp Research Inc CharIottesville Bourns Inc Trimpot Prod Div Riverside Colorado Crvstal Carp Loveland OAD Industries I nc Rancho Bernardo Silicon General Inc Garden Grove Advanced Micro Devices Inc Sunnyvale Harris Semicon Div Harris Intertype Melbourne Intel Carp Santa Clara Canadian ...

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Page 161: ...TC 0 400 1 RESISTOR 1M 51 25W CF TC 0 800 RESISTOR 1K 51 25W CF TC 0 400 RESISTOR 1K 51 25W CF TC 0 400 1 RESISTOR 1 0K 51 25w CF TC 0 400 RESISTOR 2K 51 25W CF TC 0 400 1 RESISTOR 47 51 25W CF TC 0 400 1 NETWORK RES 8 SIP 1 0K OHM X 7 1 5 CONNECTOR SGL CONT PIN 1 1 4 MM BSC SZ SO 2 IC CNTR TTL ALS BIN SYNCHRO 1 SW ASSY BW 1 IC GATE TTL ALS NAND QUAD 2 INP 1 PROGRAMMED PAL 1 IC GATE TTL ALS AND QU...

Page 162: ...A2C 1 09 C 1 1 0 0 1 60 457 1 8 CAPACITOR FXD 1 UF 80 20 50VDC CER 04222 SA205E1 04ZAA A2C l 1 2 C 1 13 0 1 6 0 4571 8 CAPACITOR FXD 1 UF 80 20 50VDC CER 04222 SA205 E 1 04ZAA A2C20 4 C205 0 1 6 0 45 7 1 8 CAPACITOR FXD 1 UF 80 20 50VDC CER 04222 SA205E1 04ZAA A2C207 0 1 6 0 457 1 8 CAPACITOR FXD 1 UF 80 20 50VDC CER 04222 SA205 E 1 04ZAA A2C209 C212 0 1 6 0 457 1 8 CAPACITOR FXD 1 UF 80 20 50VDC ...

Page 163: ... OHM X 9 1 NETWORK RES 1 0 SIP 4 7K OHM X 9 NETWORK RES 1 0 SIP 2 2K OHM X 9 1 SWITCH PB SPDT MOM CONNECTOR SGL CONT PIN 1 1 4 MM BSC SZ SQ 1 IC MPU CLK FREQ 8MHZ INSTRUCTION IC FF TTL ALS D TYPE POS EDGE TRIG COM 1 IC DCDR TTL F 3 TO 8 LINE 1 PROGRAMMED EPROM 2 SOCKET IC 28 CONT DIP DIP SLDR 8 IC CMOS 65536 6 4K STAT RAM 1 50 NS 3 S IC CMOS 65536 64K STAT RAM 1 50 NS 3 S 1 IC TRANSCEIVER TTL S IN...

Page 164: ...50VDC CER CAPACITOR FXD 1 UF 80 20 50VDC CER CAPACITOR FXD 1 UF 80 20 50VDC CER 1 CONN POST TYPE 1 25 P IN SPCG 5 CONT 1 CONN POST TYPE 1 00 P IN SPCG 3 CONT 40 SOCKET IC 28 CONT DIP DIP SLDR 1 CONN POST TYPE 1 00 P IN SPCG 1 20 CONT 41 RESISTO R 20 1 1 25W F TC 0 1 00 12 RESISTOR ZERO OHMS 22 AWG LEAD DIA RESISTOR ZERO OHMS 22 AWG LEAD DIA 4 RESISTOR lK 1 1 25W F TC 0 1 00 RESISTOR ZERO OHMS 22 A...

Page 165: ...0 20 50VDC CER 04222 SA205E1 04ZAA 4C26 0 1 60 457 1 8 CAPACITOR FXD 1 UF 80 20 50VDC CER 04222 SA205 E1 04ZAA 4C28 C29 0 1 6 0 4571 8 CAPACITOR FXD 1 UF 80 20 50VDC CER 04222 SA20 5 E 1 0 4ZAA 4C31 0 1 6 0 457 1 8 CAPACITOR FXD 1 UF 80 20 50VDC CER 04222 SA20 5 E 1 04ZAA WC33 C34 0 1 6 0 457 1 8 CAPACITOR FXD 1 UF 80 20 50VDC CER 04222 SA205 E1 04ZAA 4C36 C38 0 1 6 0 457 1 8 CAPACITOR FXD 1 UF 80...

Page 166: ...D EPROM IC FF TTL ALS D TYPE POS EDGE TRIG OCTL 1 IC TRANSCEIVER TTL ALS BUS OCTL IC FF TTL ALS D TYPE POS EDGE TRIG OCTL 1 IC DRVR TTL LS LINE DRVR OCTL PROGARMMED PROM IC SHF RGTR TTL LS R S PRL IN PRL OUT 4 IC FF TTL LS D TYPE POS EDGE TRIG COM 1 PROGRAMMED PAL 1 IC DRVR TTL LS LINE DRVR OCTL 4 IC SHF RGTR TTL LS R S PRL IN PRL OUT 1 IC PERIP HERAL INTERFACE ADAPTER PIA 1 IC COMPTR TTL LS MAGTD...

Page 167: ...3 SBR5 303 eJ2 J6 1 25 1 4670 2 5 CONN POST TYPE 1 00 PIN SPCG 3 CONT 22526 65500 1 0 3 EJ7 1 25 1 6 5 1 5 8 1 CONN POST TYPE 1 OO PIN SPCG 6 CONT 22526 656 1 0 1 06 iMP600 0356 1 4 1 1 0 1 8 6 HEAT SINK 28480 0356 1 4 1 1 0 1 eMP601 1 460 1 087 2 24 SPRING CPRSN 24 IN OD 375 IN OA LG MUW 84 30 LC 029C l MW iMP685 1 200 1 0 1 1 2 6 SOCKET ADAPTER 6 5 CONT SQUARE DIP SLDR AO l l 02 C506 5 0 1 TG P ...

Page 168: ... AM95 1 7A 5PC IC D AM95 1 7A 5PC 1 IC LCH TTL ALS TRANSPARENT NEG EDGE TRIG IC TRANSCEIVER TTL ALS BUS OCTL IC TRANSCEIVER TTL LS BUS OCTL 2 FLTR CONTROLLER IC TRANSCEIVER TTL LS BUS OCTL IC TRANSCEIVER TTL ALS BUS OCTL IC TRANSCEIVER TTL ALS BUS OCTL IC TRANSCEIVER TTL LS BUS OCTL FLTR CONTROLLER DECIMATION FLTR 1 PROGRAMMED PAL 1 IC GATE TTL ALS OR QUAD 2 INP 4 IC LCH TTL ALS D TYPE OCTL 1 IC B...

Page 169: ... TTL ALS 8 TO l LINE IC FF TTL ALS D TYPE POS EDGE TRIG 1 JMPR REM 0 25P 1 CRYSTAL QUARTZ 4 9 1 520 MHZ HC 1 8 U HLDR 2 PIN GRV 062 IN DIA 25 IN LG STL 2 EXTR PC BD GRN POLYC 062 IN BD THKNS 1 ASSY FPP 50 CAPACITOR FXD 1 UF 80 20 50VDC CER 1 CAPACITOR FXD 1 00UF 75 1 0 25VDC AL 4 CONN POST TYPE 1 00 PIN SPCG 3 CONT 5 CONN POST TYPE 1 00 PIN SPCG 6 CONT CONN POST TYPE 1 00 PIN SPCG 6 CONT CONN POST...

Page 170: ... TTL F OR QUAD 2 INP 1 PROGRAMMED PAL IC FF TTL ALS D TYPE POS EDGE TRIG COM 1 IC GATE TTL ALS AND QUAD 2 INP IC FF TTL ALS D TYPE POS EDGE TRIG 1 IC BFR TTL ALS NAND QUAD 2 INP 1 IC DRVR TTL ALS BUS OCTL IC FF TTL ALS D TYPE POS EDGE TRIG COM 1 IC COMPTR TTL LS MAGTD 2 INP 8 BIT IC FF TTL ALS D TYPE POS EDGE TRIG COM 2 PIN GRV 062 IN DIA 25 IN LG STL 2 EXTR PC BD GRN POLYC 062 IN BD THKNS 1 PC BD...

Page 171: ...F LINE DRVR OCTL 2 IC CNTR TTL LS BIN UP DOWN SYNCHRO IC CNTR TTL LS BIN UP DOWN SYNCHRO IC TRANSCEIVER TTL ALS BUS OCTL IC GATE TTL F NAND QUAD 2 INP IC TRANSCEIVER TTL ALS BUS OCTL IC BIDIRECTIONAL BUS TRANSCEIVER 8 WIDE 2 IC MUXR DATA SEL TTL F 2 TO 1 LINE QUAD 7 JMPR REM 025P 2 PIN GRV 062 IN DIA 25 IN LG STL 2 EXTR PC BD GRN POLYC 062 IN BD THKNS 1 JUMPER 1 6 CKT CONN 1 CONN POST TYPE 1 00 PI...

Page 172: ...M 1 IC LCH TTL LS COM CLEAR 8 BIT 1 IC MUXR DATA SEL TTL LS 8 TO 1 LINE 1 PROGRAMMED PAL 1 IC FF TTL LS J K BAR POS EDGE TRIG 2 IC CNTR TTL LS BIN SYNCHRO POS EDGE TRIG 1 IC BFR TTL ALS NAND QUAD 2 INP 1 IC GATE TTL ALS NAND QUAD 2 lNP 2 lC FF TTL ALS D TYPE POS EDGE TRIG 1 IC GATE TTL ALS OR QUAD 2 INP IC I NV TTL ALS HEX 2 IC DCDR TTL F 3 TO 8 LINE 2 IC GATE TTL ALS AND QUAD 2 INP 1 PROGRAMMED P...

Page 173: ...C CER 04222 SA205El 04ZAA 1 5C R 1 CR3 1 9 90 0487 7 LED LAMP LUM INT 2MCD BVR 5V 28480 1 990 0487 1 5CR4 1 990 0485 5 4 LED LAMP LUM INT 2MCD IF 30MA MAX BVR 5V 28480 1 990 0485 1 5CR5 CR6 1 9 90 0487 7 LED LAMP LUM INT 2MCD BVR 5V 28480 1 990 0487 1 5CR7 1 990 0486 6 3 LED LAMP LUM INT 2MCD IF 25MA MAX BVR 5V 28480 1 990 0486 1 5CR8 CR 1 1 1 990 0487 7 LED LAMP LUM INT 2MCD BVR 5V 28480 1 990 04...

Page 174: ...YSTAL QUARTZ 4 0000 MHZ HC 1 8 U HLDR STAND L E D JMPR REM 025P JUMPER 1 6 CKT CONN DI SPLAY ASSY CAPACITOR FXD 1 UF 80 20 50VDC CER CAPACITOR FXD 22UF l 0 35VDC TA CAPACITOR FXD 1 UF 80 20 50VDC CER DIODE GEN PRP 1 N4002 1 00V l A DO 41 DIODE ZNR l N5339B 5 6V 5 PD 5W IR l UA CONN POST TYPE 2 5 PIN SPCG 2 CONT CONN POST TYPE 1 00 PIN SPCG 40 CONT PTC THERMISTER RESISTOR lK 1 1 25W F TC 0 1 00 RES...

Page 175: ...F 80 20 50VDC CER CAPACITOR FXD 22UF 50 1 0 50VDC AL CAPACITOR FXD 1 UF 80 20 50VDC CER CAPACITOR FXD 22UF 50 1 0 50VDC AL CAPACITOR FXD 470PF 1 0 lKVDC CER CAPACITOR FXD 1 UF 80 20 50VDC CER CAPACITOR FXD 0 1 UF 1 00 0 50VDC CER CAPACITOR FXD 1 UF 80 20 50VDC CER DIODE SWITCHING 80V 200MA 2NS DO 35 LED LAMP ARRAY LUM INT 200UCD IF 5MA MAX IC MISC 3 TO 46 PKG DIODE SWITCHING 80V 200MA 2NS DO 35 VO...

Page 176: ...RMR 1 K 1 0 C TOP ADJ 1 TRN 73 1 38 72PR 1 K 1 05B A1 8R2 R3 0757 0280 3 1 4 RESISTOR l K 1 1 25W F TC 0 1 00 19701 5033R A1 8R4 0757 0413 6 1 RESISTOR 2 2 1 K 1 1 25W F TC 0 1 00 1 9 701 5033R A 1 8 R5 0757 0428 1 1 RESISTOR 1 62K 1 1 25W F TC 0 1 00 1 9 701 5033R A18R6 0151 0443 0 1 RESISTOR 1 1 K 1 1 25W F TC 0 1 00 1 9 7 0 1 5033R A 1 8 R 7 0757 0442 9 RESISTOR 1 0K 1 1 25W F TC 0 1 00 19701 5...

Page 177: ...1 1 25W F TC 0 1 00 1 9 7 0 1 5033R 1 8R202 0757 0442 9 RESISTOR 1 0K 1 1 25W F TC 0 100 19701 5033R 18R203 0698 3279 0 RESISTOR 4 99K 1 1 25W F TC 0 1 00 1 9 7 0 1 5033R 18R204 0698 3 1 6 2 0 2 RESISTOR 4 6 4K 1 1 25W F TC 0 1 00 1 9701 5033R 18R205 R206 0698 0082 7 2 RESISTOR 4 6 4 1 1 25W F TC 0 1 00 1 9701 5033R 18R207 0698 3 1 6 2 0 RESISTOR 4 6 4K 1 1 25W F TC 0 1 00 1 9701 5033R 18R209 0698...

Page 178: ...5K 1 1 25W F TC 0 1 00 RESISTOR 499 1 1 25W F TC 0 1 00 RESISTOR 20K 1 1 25W F TC 0 1 00 RESISTOR 1 00K 1 1 25W F TC 0 1 00 TUBE ELECTRON SURGE V PTCTR PWR XFMER 1 28KHZ INDUCTOR FIXED CURRENT SENSE INDUCTO R L BIAS XFMR GATE DRIVE TFMR CONNECTOR SGL CONT PIN 1 1 4 MM BSC SZ SQ IC D 74HC 1 3 3 CMOS NANDGT P 1 6 I C COMPARATOR G P QUAD 1 4 DIP P PKG IC GATE CMOS 74HC NAND QUAD 2 INP IC COMPARATOR G...

Page 179: ... CER CAPACITOR FXO 5 6PF 5PF 1 00VOC CER CAPACITOR FXO 1 30PF 5 1 00VOC CER CAPACITOR FXD 1 3 00PF 1 50VOC CER CAPACITOR FXO 1 UF 80 20 50VOC CER CAPACITOR FXO 250PF 1 1 00VDC MICA CAPACITOR FXO 1 UF 80 20 50VDC CER CAPACITOR FXO 1 2PF 5 1 00VDC CER 0 30 CAPACITOR FXO 1 UF 80 20 50VOC CER CAPACITOR FXO 1 UF 20 25VDC CER CAPACITOR FXO 1 UF 80 20 50VOC CER CAPACITOR FXO 1 UF 80 20 50VOC CER CAPACITO...

Page 180: ... TC 0 25 RESISTOR 47 5 25W CF TC 0 400 2 RESISTOR 2K 1 1 25W F TC 0 25 3 RESISTOR lK 1 1 25W F TC 0 25 1 RESISTOR 32 4 1 1 25W F TC 0 1 00 1 RESISTOR 3 2 4K 1 1 25W F TC 0 1 00 2 RESISTOR l K 1 1 25W F TC 0 1 00 RESISTOR lK 1 1 25W F TC 0 1 00 1 RESISTOR 7 32K 1 1 25W R TC 0 1 00 RESISTOR 1 00 1 1 25W F TC 0 1 00 RESISTOR 2K 1 1 25W F TC 0 25 RESISTOR 200 1 1 25W F TC 0 25 RESISTOR l K 1 1 25W F T...

Page 181: ...CLEAR STOR 8 BIT 1 IC I NV TTL ALS HEX 1 I C COMPARATOR GP DUAL 1 4 DIP P PKG 2 JMPR REM 025P JMPR REM 025P 1 TERMI NAL STUD SPCL FDTHRU PRESS MTG 1 PIN EXTR 1 PC BD TRIGGER 1 CAPACITOR FXD 6 8UF l 0 35VDC TA 1 CAPACITOR FXD 22UF l 0 1 5VDC TA 1 CAPACITOR FXD l UF l0 35VDC TA 2 CAPACITOR FXD 022UF 5 200VDC POLYE 45 CAPACITOR FXD 1 UF 80 20 50VDC CER CAPACITOR FXD 1 0PF 5 1 00VDC CER 0 30 CAPACITOR...

Page 182: ...5 DO 35 PD 4W TC 025 047 1 3 SZ30035 008 A3 1 CR204 0757 0274 5 1 RESISTOR 1 2 1 K 1 1 25W F TC 0 1 00 19701 5033R A3 1 CR30 1 CR302 1 9 0 1 0050 3 DIODE SWITCHING 80V 200MA 2NS DO 35 07263 FDH 6308 A31 CR303 CR304 1 902 0958 2 DIODE ZNR 1 0V 5 DO 35 PD 4W TC 0751 047 1 3 SZ30035 0 1 6 A3 1 CR 4 0 1 1 9 0 1 0040 1 1 DIODE SWITCHING 30V 5 0MA 2NS DO 35 07263 FDH1 088 A 3 1 CR402 CR403 0 1 22 0162 5...

Page 183: ... 7 0 1 5033R 3 1 R 1 20 0698 3 1 6 0 8 RESISTOR 3 1 6K 1 1 25W F TC 0 1 00 1 9 7 0 1 5033R 3 1 R 1 2 1 0757 0280 3 RESISTOR 1K 1 1 25W F TC 0 1 00 19701 5033R 3 1 R1 22 0698 3 1 6 0 8 RESISTOR 3 1 6K 1 1 25W F TC 0 1 00 1 9 7 0 1 5033R 3 1 R1 2 3 0698 3 1 5 7 3 RESISTOR 1 9 6K 1 1 25W F TC 0 1 00 1 9701 5033R 3 1 R1 2 4 0757 0394 0 RESISTOR 5 1 1 1 1 25W F TC 0 1 00 19701 5033R 3 1 R1 2 5 0757 04 ...

Page 184: ... 1 1 25W F TC 0 1 00 1 9 CONNECTOR SGL CONT PIN 1 1 4 MM BSC SZ SQ 1 IC OP AMP WB TO 99 PKG 1 ANALOG SWITCH 4 SPST 1 6 CBRZlSDR 1 IC DCDR TTL LS 2 TO 4 LINE DUAL 1 IC SHF RGTR TTL LS SERIAL IN SERIAL OUT 1 IC OP AMP LOW DRIFT TO 99 PKG 1 D A 8 BIT 16 CERDIP BPLR 2 IC COMPARATOR HS 1 4 DIP P PKG 1 IC GATE TTL LS EXCL OR QUAD 2 INP 1 IC DRVR TTL ALS BUS OCTL 1 IC OP AMP LOW BIAS H IMPD DUAL 8 DIP P ...

Page 185: ...FXD 22UF l 0 3SVDC TA CAPACITOR FXD 1 UF 80 20 SOVDC CER CAPACITOR FXD l UF 1 0 35VDC TA CAPACITOR FXD 4 7UF 20 1 0VDC TA CAPACITOR FXD 1 UF 80 20 SOVDC CER CAPACITOR FXD 22UF l 0 35VDC TA CAPACITOR FXD l SPF 5 1 00VDC CER 0 30 CAPACITOR FXD 1 UF 80 20 SOVDC CER CAPACITOR FXD 1 UF 80 20 SOVDC CER 1 CAPACITOR FXD 470PF S 1 00VDC CER 1 CAPACITOR FXD 2 2UF l 0 20VDC TA CAPACITOR FXD 1 UF 80 20 SOVDC ...

Page 186: ...25W F TC 0 1 00 1 9701 5 033R A32R408 2 1 00 3054 6 1 RESISTOR TRMR 50K 1 0 C SIDE ADJ 1 7 TRN 73 1 38 8 9PR50K A32R409 0698 6377 5 1 RESISTOR 200 1 1 25w F TC 0 25 9 1 637 CMF 55 1 T 9 A32R4 10 0698 4 4 1 2 5 1 RESISTOR 1 4 3 1 1 25W F TC 0 100 9 1637 CMF 55 1 T l A32R4 1 1 0698 3 1 6 1 9 RESISTOR 38 3 K 1 1 25W F TC 0 1 00 1 9701 5033R A32R4 12 0757 1 094 9 RESISTOR 1 47K 1 1 25W F TC 0 1 00 1 9...

Page 187: ...SHF RGTR TTL LS ASYNCHRO SERIAL IN 5 IC OP AMP LOW NOISE 8 DIP P PKG 1 IC V RGLTR FXD NEG 4 8 5 2V TO 220 PKG 1 IC OP AMP WB TO 99 PKG 1 IC PRCN DUAL 8 TO 99 PKG 1 IC OP AMP LOW BIAS H IMPD TO 99 PKG 1 ANALOG MULTIPLEXER 6 CHNL 16 DIP P IC OP AMP WB TO 99 PKG 2 IC COMPARATOR GP DUAL 1 4 DIP P PKG IC OP AMP LOW NOISE 8 DIP P PKG IC COMPARATOR GP DUAL 1 4 DIP P PKG 1 IC GATE TTL ALS NAND QUAD 2 INP ...

Page 188: ...R2 DYS A33C6 1 1 C 6 1 2 0 1 6 0 4571 8 CAPACITOR FXD 1 UF 80 20 50VDC CER 04222 SA205El 04ZAA A33CR 1 00 1 9 02 0654 5 4 DIODE ZNR 33V 5 PD lW IR 5UA 047 1 3 S24 0 1 4 5 025 A33CR 1 0 l 1 9 0 1 005 0 3 8 DIODE SWITCHING 80V 200MA 2NS DO 35 07263 FDH 6308 A33CR 1 02 CR 1 0 3 1 9 0 1 0579 1 4 DIODE SWITCHING 40V 20MA 300NS DO 7 07263 FJT l l 00 A33CR 1 0 4 1 9 0 1 0050 3 DIODE SWITCHING 80V 200MA 2...

Page 189: ...R 2 IC SHF RGTR TTL LS ASYNCHRO SERIAL I N 5 IC OP AMP LOW NOISE 8 DIP P PKG 1 IC V RGLTR FXD NEG 4 8 5 2 V TO 220 PKG 1 IC OP AMP WB TO 99 PKG 1 IC PRCN DUAL 8 TO 99 PKG 1 IC OP AMP LOW BIAS H IMPD TO 99 PKG 1 ANALOG MULTIPLEXER 6 CHNL 16 DIP P IC OP AMP WB TO 99 PKG 2 IC COMPARATOR GP DUAL 1 4 DIP P PKG IC OP AMP LOW NOISE 8 DIP P PKG IC COMPARATOR GP DUAL 1 4 DIP P PKG 1 IC GATE TTL ALS NAND QU...

Page 190: ...R2 DYS A33C6 1 1 C 6 1 2 0 1 6 0 4571 8 CAPACITOR FXD 1 UF 80 20 50VDC CER 04222 SA205El 04ZAA A33CR 1 00 1 902 0654 5 4 DIODE ZNR 33V 5 PD l W IR 5UA 047 1 3 SZ401 45 025 A33CR 1 0 1 1 9 0 1 0050 3 8 DIODE SWITCHING 80V 200MA 2NS DO 35 07263 FDH 6308 A33CR 1 02 CR 1 0 3 1 9 0 1 0579 1 4 DIODE SWITCHING 40V 20MA 300NS DO 7 07263 FJT 1 1 00 A33CR 1 04 1 9 0 1 0050 3 DIODE SWITCHING 80V 200MA 2NS DO...

Page 191: ...A 3R207 0757 0 123 3 RESISTOR 34 8K 1 1 25W F TC 0 1 00 1 9701 5033R A 3R208 R209 0757 0401 0 RESISTOR 1 00 1 1 25W F TC 0 1 00 19701 5033R A 3R2 10 0757 0 1 23 3 RESISTOR 34 8K 1 1 25W F TC 0 1 00 19701 5033R A 3R2 1 1 0757 040 1 0 RESISTOR 100 1 1 25W F TC 0 1 00 1 9701 5033R A 3R2 1 2 2 1 00 3874 8 RESISTOR TRMR 5K 10 C TOP ADJ 1 7 TRN 32997 3299W DM3 502 A 3 2 1 3 0757 0280 3 RESISTOR l K 1 1 ...

Page 192: ... 00 0K OHM X 1 IC OP AMP LOW NOISE 8 DIP P PKG IC OP AMP LOW NOISE 8 DIP P PKG 2 TRANSISTOR ARRAY 1 6 PIN PLSTC DIP 3 IC SHF RGTR TTL LS ASYNCHRO SERIAL IN 4 IC OP AMP LOW NOISE 8 DIP P PKG 1 ANALOG MULTIPLEXER 8 CHNL 16 CBRZlSDR IC OP AMP LOW NOISE 8 DIP P PKG IC OP AMP LOW NOISE 8 DIP P PKG 1 IC BFR TTL LS NOR QUAD 2 INP 1 IC COMPARATOR GP QUAD 1 4 DIP P PKG IC SHF RGTR TTL LS ASYNCHRO SERIAL IN...

Page 193: ...PLY 28480 03562 0 4 1 06 MP 02 03562 04 1 07 7 1 COVER 1 345A DISPLAY 28480 03562 04 1 07 MP 0 3 03562 48306 0 1 RETAINER DIGITAL BOARD 28480 03562 48306 MP 04 03562 0 1 2 1 2 9 1 RETAI NER ANALOG BOARD 28480 03562 0 1 2 1 2 MP 05 500 1 0 4 4 1 2 2 TRIM SIDE 28480 500 1 044 1 MP 0 6 5040 7201 8 4 FOOT 28480 5040 7201 MP 07 5040 7202 9 1 TRIM TOP 28480 5040 7202 MP 09 5060 9805 4 2 STRAP HANDLE 284...

Page 194: ...AP RANGE 28480 504 1 4522 MP657 504 1 4523 3 1 KEY CAP AUTO SEQ 28480 5041 4523 MP658 5041 4524 4 1 KEY CAP X 28480 5041 4524 MP659 5041 4525 5 1 KEY CAP Y 28480 504 1 4525 MP660 5041 4526 6 1 KEY CAP CAL 28480 5041 4526 MP66 1 504 1 4527 7 1 KEY CAP VIEW INPUT 28480 504 1 4527 MP662 504 1 4565 3 1 KEY HALF 28480 504 1 4565 W1 03562 6 1 6 0 1 6 2 CABLE INPUT 28480 03562 6 1 6 0 1 03562 20601 0 1 S...

Page 195: ...G FOR 3 8 SCR 3 NUT HEX DBL CHAM 1 5 32 32 THD 3 CLAMP CABLE 1 87 DIA 7 35 WD NYL 2 WASHER FL MTLC NO 6 1 47 IN ID 2 WASHER FL MTLC 5 1 6 IN 375 IN ID 2 SCREW MACH M3 5 X 0 6 6MM LG PAN HO 2 SCREW MACH M3 5 X 0 6 1 0MM LG 2 SCREW SKT HD CAP M3 X 0 5 8MM LG 2 RVT BLD DMHD 1 250 06GRP AL 2 NUT HEX DBL CHAM 1 2 28 THD 1 25 IN THK 2 LABEL WARNING 1 25 IN WD 2 7 5 IN LG 2 GROMMET RND 375 IN ID 5 IN GRV...

Page 196: ......

Page 197: ...ay Interface A1 8 Power Supply A22 HP l B A30 Analog Source A31 Trigger A32 A34 ADC A33 A35 Input Figures Title Local Oscillator Schematic Revision A Local Oscillator Component Locator Revision A Digital Filter W7 Position Revision A Power Supply Component Locator Revision B Power Supply Component Locator Revision A Power Supply Schematic Revisions A B Analog Source Component Locator Revision A Tr...

Page 198: ......

Page 199: ...keep the manual up to date periodically request the most recent supplement available from the nearest Hewlett Packard office see sales and support offices listing at the back of this manual 5 3 FORMAT Design and component changes within the instrument are noted by the il symbol When this symbol appears refer tothe appropriate assembly heading in this section forthe manual changes 5 4 A1 DIGITAL SO...

Page 200: ...0 0638 U33 1 200 0639 Revision A differs from revision B as follows 1 Signature analysis connector J1 is mislabeled I t should be labeled as follows J1 1 GND J1 3 ClK J1 4 STP J1 4 SRT 2 Change the following part numbers in the Replaceable Parts list U20 to 03562 60342 U29 to 03562 60341 3 In table A4 2 change the signatures for U20 and U29 as follows Component Pin Signature Component Pin Signatur...

Page 201: ... D3 I A7 D4 14 15 A8 D5 A9 D6 16 19 AIO D7 17 18 A l l MSB 21 2C AI2 cs NOTE E20 AND E29 ARE FOUR PI N EXTENSIONS ADJACENT TO U20 AND U29 TO ALLOW USE OF 2a P I N EPROMS OR ROMS LOAD 0 0HM RESISTORS FOR R21 AND R23 TO USE 24 P I N DEVICES O R FOR R20 AND R22 T O U S E 2a P IN DEVICES FOR UNLATCHED ADDRESSES EPROM LOAD R25 FOR LATCHED ADDRESS LOAD R26 Figure 5 A4a Local Oscillator Schematic Revisio...

Page 202: ...sion E Revisions A through D The following components are in sockets Component Socket Part Number U107 1 200 0607 U109 1 200 0638 U11 0 1 200 0638 US1 2 1 200 0638 U206 1 200 0700 U306 1 200 0700 Revisions A and B All jumpers are identified with a W rather than a Revs A and B later Revs W002 j002 W003 j003 W004 j004 WOOS JOOS W006 j006 W007 j007 Revision A Make the following changes 1 Polarity mar...

Page 203: ...sition set the jumpers as shown in figure 5 A5 W7 rol 0 i N POSIT ION l2J O T nO ol JUMPERS I N TEST Figure S AS Digital Filter W7 Position Revision A 5 9 A6 DIGITAL FILTER CONTROLLER Current revision C Previous revisions are all electrically the same as revision C Revision B Component U208 is in a socket part number 1 200 0700 Revision A Make the following changes 1 The following components are i...

Page 204: ...ntical to revision B The test jumpers J3 through J9 are not labeled on revision A Normal N position is to the left test T position to the right 5 1 2 A9 FAST FOURIER TRANSFORM PROCESSOR Current revision B Previous revisions Revision A is electrically identical to revision B On the revision A component locator C117 is located directly above U117 5 1 3 A1 2 MOTHER BOARD Current revision B Previous r...

Page 205: ...to 0180 0374 10 flF R116 to 0757 0401 1 00 OHM R126 and R304 to 0757 0442 10K b Delete the following components C527 C528 C529 and C530 CR530 CR531 CR532 and CR533 c Add the following components R104 0757 0280 1 K R114 0698 3228 49 9K R118 0698 3279 4 99K R208 0757 0465 100K Q103 and Q104 1854 021 5 NPN 2N3904 Q205 1853 0036 PNP 2N3906 U100 1820 3183 74HC03 CMOS 2 Remove A18 component locator revi...

Page 206: ......

Page 207: ...MODEL 3562A CR Cl ...

Page 208: ...1 R4 1 R413 C am J l CWLJ MANUAL BACKDATI NG 1 R a2 c a c a3 T3 l J I J L J L J LJ Figure 5 At Ba Power Supply Component Locator Revision B 5 9 5 1 0 ...

Page 209: ...MODE L 3562A Cl ...

Page 210: ... MANUAL BACKDATING 1 Rm _ _ _ _ _ _ _ l Ri92 Ci93 T3 l J I J L l L l U i o Figure 5 At ab Power Supply Component Locator Revision A 5 11 5 12 ...

Page 211: ... ...

Page 212: ... J1 FROM U2 13 _ _ P M RU P o FROM Ul04 13 _ _ PW RD NL CO FROM Ul04 14 _ _ OT EMPl o FROM Ul00 9 TO A12 Figure 5 A18c Power Supply SchematIc Revisions A and B 5 1 3 5 14 ...

Page 213: ...r A1 a pQWERSuP PLY I 03562 66518 REV A REV 8 8MPOUT 58 58 FRONT REAR P ANEL ii O N ...

Page 214: ... C401 8S1 15ISI t 1 J400 ...

Page 215: ...s revisions Revision B is electrically identical to revision C The revision B component locator differs from revision C in the spacing of three groups of axial I ad components These components are located to the right of U600 U456 and U503 U4 5 9 1 U451 1 Figure A30 Analog Source Component Locator Revisions B C C355 U351 13 J55 9 c J 5 15 ...

Page 216: ...B Previous revisions Revision A differs from revision B as follows see figures 5 A31 a and 5 A31 b I 1 _ us _ s8 I _ 1 L l L J _ USS _ 7 _ 1 _ us_ ss 1 _ us _ ss 1 1ij II Q I X I I I 1 9 1 9 9 S 9 1I J 1 I e o Figure 5 A3 1 a Trigger Component Locator Revision A 5 16 ...

Page 217: ... ...

Page 218: ... JS2 19 20 _ JS4 19 20 i r A1 J1 1B ASO JSO 40 AS2 JS2 2S 24 AS4 JS4 2S 24 Ai J1 U9 120 A4 J4 U9 120 A5 J5 U4 AB JB US A1B N1S 1 Figure 5 A3 1 b Trigger Schematic Revision A 5 1 7 5 18 ...

Page 219: ...1 5 19 1 251 0600 MANUAL BACKDATING 2 The following test locations on revision A correspond to the test points listed for revision B Revision A Revision B Test Location Test Point U305 11 TP1 5 U507 5 TP1 6 U9 7 TP1 7 U303 8 TP1 8 CR1 05 anode TP19 3 The pulse width of RE F IN 1 25 A31 U305 11 TP1 5 is different ...

Page 220: ......

Page 221: ... ...

Page 222: ...02 5VR C610 C609 15V L604 22pF l 1 0 1 l 100pF W W tTP606 W 9 6061 1 C60B C402 1C400 l C612 V L6030 1 1 l 22pF 1 01 t 1 0 1 1 0 1 100pF W W W TP605 W W C6051 1 C607 C403 1 C401 1c611 V 2 LJi O O p O F 22PF O 1 O 1 O 1 O 1 5 _ 1 1 tTP604 30V1 C601 C600 2 L 5 6 0 0 p 2 F 4 7PF O 1 4 1 TP502 30V1 C604 C603 4 7PF 1 0 1 1 TP401 W W Figure 5 A33b Input Schematic Revision A 5 21 5 22 ...

Page 223: ...562 66533 INPUT 2 03562 66535 WHERE NOTED REV A J300 0 1 fROH fRONT PANEL W1 HP104 A30 9 HIGH INPUT SNC CENTEA A1 J 1 I C N u T l n __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ I COPYFiISHTtI 5 1985 HEWLE1 PACKAROTo ...

Page 224: ...A3 CQVLCLI A3 ...

Page 225: ...45 6 8 f 7 Floating Point Processor 6 58 6 9 A8 G lobal RAM A1 7 Display Interface 6 67 6 1 0 A9 Fast Fourier Transform Processor 6 75 6 1 1 A1 5 Keyboard 6 89 6 1 2 A1 8 Power Supply 6 95 6 1 3 A30 Analog Source 6 99 6 1 4 A31 Trigger 6 1 05 6 1 0 6 6 1 5 A32 A34 Analog Digital Converter 6 1 1 3 6 1 6 A33 A35 Input 6 1 23 6 1 7 Signal Descriptions 6 1 27 Number 6 A32a 6 A32b 6 A33 Tables Title Pa...

Page 226: ...ced to the Digital Filter Boards Zoom Implementation A5 Block Diagram A6 Block Diagram FPP Block Diagram G l obal RAM Block Diagram Displ ay Controller Interface Block Diagram Fast Fourier Transform Processor Block Diagram Address Generation Block Diagram Keyboard Block Diagram Power Supply Block Diagram Analog Source Trigger Level Block Diagram Trigger Clock Block Diagram Track Hold Input vs Outp...

Page 227: ...DEL 3562A CPU K HP I B IL I I V I I KEYBOARD l V I NPUT analog digital o signal s ignal ADC V RAM control V line DIG ITAL DISPLAY FRONT A control l ines END I NTERFACE COMMON BUS 2 6V e _ 30V Figure 6 1 Waveform Recorder 6 2 ...

Page 228: ...ociated with the FFT such as sample rate number of frequency data points time required for a complete conversion and others are all related to powers of two For example a time record is defined to be N consecutive equally spaced samples of the input where N is a multiple of 2 This time record is transformed as a complete block into a complete block of frequency lines With a Dynamic Signal Analyzer...

Page 229: ...I I digital signal ADC si nal C H AN N E L i 1 i control I I line I i I d ital analog ADC si nal signal I CHAN N E L 2 control line control lines 1 FRONT E N D I NTE RFACE J A COMMON BUS I 2 6V 5V 8V 1 5V 30V I I CPU I A A r A Figure 6 2 Two Channel Waveform Recorder with Source L H P I B A I r r I I RAM r 1 D I G I TAL D I SP LAY 6 3 6 4 ...

Page 230: ...trigger external reference in and external sample modes In figllre o 4 the analyzer becohies the HP 3S62A by a oclTiigfne localoscillafof a nd program ROM assemblies The local oscillator provides digital sine and cosine signals for the digital source and digital filter The digital source distributes the digital sine to the analog source assembly for conversion to an analog signal The digital filte...

Page 231: ...S V InO 3J nOS N I l3 3 1 1 1X3 NI 31dWVS lX3 H l 1 3 NNVH I 0 Ioe J ...

Page 232: ...nes T R I G G E R f Trigger Signal Control Li nes POW E R S U PPLY Digital Signal 2 6V SV 8V 1 SV 30V K EYBOARD D I G I TAL F I LT E R i J D I G ITAL F I LTER CONTROLLER f D I G ITAL SOURCE AND F G I N TE RFACE Figure 6 3 Two Channel Fixed Span Analyzer with Source SYST E M CPU A lI H P I B A 68000 K I I y I y FFT COMMON BUS FPP RAM I D I G ITAL D I S PLAY 6 7 6 8 ...

Page 233: ...CI I ANNEl 1 CI IANNEl 2 EXT SAMPLE IN EXT TRIGG E R R E F I N SOURCE OUT I f Q 1 MO V A33 a INPUT CHAN N E L 2 ANALOG SOURCE A30 anall signi cantl line TRI J IS L ...

Page 234: ...l r signal AS 0 j t u 03 DIG ITAL F I LTER c SYSTEM BUS 0 v CONTROLLER 3 r 00 A6 0 LOCAL OSCI LLATOR A4 r trigger signal digital sine control l ines DIGITAL SOURCE AND F E INTE RFACE A1 Figure 6 4 HP 3562A Block Diagram A2 I SYSTEM GLOBAL SYSTEM G LOBAL l H P I B r A22 PROG RAM I A3 I FFT Ag FPP A7 G LOBAL DATA RAM 64 KW AB D I SPLAY INTERFACE A1 7 I rear panel connector DIG ITAL D I S PLAY H P 1 ...

Page 235: ...T H J US 6 THD I US S LDL U3 17 LJ CLRL U3 1 2 LJ ALUCK U3 1 S LJ 5A U3 1 3 5 B U3 14 DACEN U3 16 F5LD U3 1 S LJ DACDAT U209 6 522 522 522 1 50 51 52 53 54 COUNTER 8 0 0 2 3 4 S ...

Page 236: ...u u u db co Jf u if If H ff If 56 57 58 59 510 51 1 512 51 3 51 4 51 5 51 6 51 7 51 8 51 9 520 521 522 522 522 fJ I f 7 8 9 10 11 1 2 1 3 14 1 5 0 Figure 6 A1 a Digital Source Timing 2 3 4 6 7 8 8 8 8 8 6 1 3 6 14 ...

Page 237: ...Sample Clock SAMP DS DATA oe _ _ _ _ _ BUS NOTE FULL SPA BASi BAI MODE ...

Page 238: ...I STERS i DS 2 56 MHz I MULTI PROG RAMMABLE PLlER COUNTERS I I Figure 6 A1 b Timing Contra Circuit DSE L x 1 I I BURST I CONTROL C I RCUIT 2 56 MHz MULTI L eo PLEXER N LATCH NOISE SA G EN E RATOR SS CLR LATCH _ Sample I N PU T RECEIVER 6 1 5 6 1 6 ...

Page 239: ...xt sample clock the phase circuit starts counting and counts until a trigger signal TRIGROL REMTGL SWTRIG or BURSTRIG is received If another sample clock is received before the trig ger signal the phase state machine starts the count over and continues to wait for the trigger signal clearing the counters each time a sample clock is received When a trigger signal is received the counters latch the ...

Page 240: ...r TRIGO REMTG l SWTRIG BURSTRIG From Control T1 os DATA BUS 8 Bit COU NTERS PHASE STATE MACH I N E TRIGG ER TRIGRO MULTI PLEXER _r Registers TO _ _ _ _ _ _ 1 6 18 Figure 6 A1 c Phase Resolution Circuit MODEL 3562A L BFST To LO and o FLTR cant ARMEDl To Burst Control Circuit ...

Page 241: ...ARMEDL signal from the phase resolution circuit goes low The counters only count when ARMEDL is low The ARMEDL signal also causes the burst control circuit to send the NCLK signal to the local oscillator When NCLK is received by the local oscilla or the LO is set to the starting frequency of the burst The local oscillator sends data NDAT to the digital source synchronized to NCLK The data is proce...

Page 242: ...random sequence that is used for band limited random noise and burst noise signals The noise generator is a 32 bit shift register with feedback to generate a pseudorandom sequence This sequence is multiplied by a squared analog random signal This randomizes the feedback of the shift register The analog ran dom noise is a zener diode biased so that it is barely on and is thus noisy The output of th...

Page 243: ...ontrol data word CNTLD If it is 1 the digital source is sending the word If it is 0 the digital source is ready to send another control data word This signal is from the control register to the status registers CONTINUOUS _ When this control signal is high the digital source keeps the A30 Analog Source enabled When low the analog source is gated by the burst control circuit CONTROL Signal from the...

Page 244: ...ivided sample rate Refer to DA DB for chart ENABLE LOAD Active Low Enable load from the control registers determines when the serial command word CNTLD is sent to the A30 Analog Source the A31 Trigger The A33 A35 Input boards or the A32 A34 ADC boards FREERUN Signal from the control registers When in the freerun mode this signal is high LOAD These signals are used to monitor the load pulses to the...

Page 245: ...0 MHz clock the LO serial data clock and the serial data shift clock DATA REQUEST This signal is used when in the self test mode as the data request line TEST This signal enables the self test signals to be multiplexed into the data paths and clock lines This signal must be low for the assembly to function in the normal mode TEST LOCAL OSCILLATOR DATA This signal is used as the LO serial data for ...

Page 246: ......

Page 247: ... A8L J V System Data Bus DO TO D1 5 V ENABLEL RESETL WRITEL DEVICE INSTRUCTION 2 V 1 ADDRESS COMPARATOR STESl 1 1 DATA A BUS DS Data Bus BUFFERS t Write To Control S J RESL I f DEVICE DEVICE DECO D E R I tOO DECO D E R BUFFE R PAL ...

Page 248: ...UIT 11 BFST ARMEDL From All To LO and Functional D FLTR CONT Blocks t roR MULT I PLI E R 6 A1 e Digital Source Block Diagram SELCNTRSL l Noise Generator LD1 6L Control L BURST CONTROL to SYNC BURSTEN NCLK Command Word CONTROL to Ana REG ISTE RS V To All Functional Blocks DACDAT Data to Analog Source Inp log Source ut Boards ger Board C Boards Trig AD 6 25 6 26 ...

Page 249: ...n the assembly handshakes with the system CPU Most assemblies use the asynchronous signal Data Transfer Acknowledge DTACKL to handshake with the system CPU The exception is the A4 Local Oscillator It uses the synchronous signal Valid Peripheral Address VPAL to handshake with the system CPU Off Board Operations The system processor uses the system bus control system address drivers system data buff...

Page 250: ...devices to access the global RAM For this operation the system CPU has 1 6 address lines 16 data lines and 4 control lines connected to the global bus The system CPU s global address bus connection CA1 L to CA16L is an extension of the lower 1 6 bits of the CPU address bus When the system CPU addresses a global RAM memory location the system CPU s address decoder asserts the global request CLRQTL ...

Page 251: ...handshake is completed DTACKL or VPAL is received or the counter reaches its terminal count If the timer reaches the term inal count of 32 p s before the handshake is completed the bus error line BE RRL to the system processor is asserted to abort the current bus cycle The system processor then begins processing for the bus error Bus errors are entered in the fault log along with the name of the a...

Page 252: ...CPU CLOCK PRIORITY I NTERRUPT E N CO DER A STATUS v 8 MHz SYSTEM PROCESSOR INTERRUP IRQT 2L to IRQT 7L IRQT 6L _ CPU DATA BUS Dc to I I _lJCPU ADDRESS Iffi57i 3 UDSL LDSL R WL ADDRESS DECODER GLR QTL 3 HAND SHAKE LDTACKL LVPAL __ _ 1 BERRL ERROUT I BUS T I M E OUT od Figure 6 1 ...

Page 253: ...R R WL GLOBAL BUS DRIVER G LOBAL BUS LATCH I I I I GLOBAL GLRDEN BUS GLSTB I 1 CONTROL re to D7 CPU DATA BUS D to D7 H P I B ICs CPU ADDRESS BUS A1to A3 HANDSHAKE LINES ystem CPu HPIS Slock DIagram y 7 v A TO SYSTEM BUS SYSTEM ADDRESS BUS A1 Lto A23L v SYSTEM DATA BUS D Lto D1 5L GLOBAL ADDRESS BUS GAIL TOGA16L MG68L GLOBAL DATA BUS GD L TO GD15L GR GWL GDSL HPIB DTACKL VPAL MR68L REMTG L MG68L 6 ...

Page 254: ...d was addressed 2 Enables the ROM Decoder 3 Enables the Data Bus Driver ROM Decoder The ROM decoders U21 U22 and U23 are 1 of 8 decoders They generate the chip enable CE1 L through CE20L signals by decoding system address lines A1 6 through A21 The chip enable signal causes the selected ROM pair to put data on the data bus Delay U1 3 and U1 4 are used to delay the DTACKL signal based on the speed ...

Page 255: ... the ROMSELL signal the ROM decoder issues a chip enable C E signal to the appropriate ROM pair The C E signal enables the ROM pair to put data on the ROM data bus The ROMSE LL signal gates the data through the data bus drivers onto the system data bus and returns DTACKL data ack nowledge to the system CPU Internal Signal Descriptions CEl l through CE20l C lK ROMSELl Chip enable 1 20 active low En...

Page 256: ...sed 2 Enables the ROM Decoder 3 Enables the Data Bus Driver ROM Decoder The ROM decoders U21 U22 and U23 are 1 of 8 decoders They generate the chip enable C E1 L through CE20L signals by deco ding system address l ines A1 6 through A21 The chip enable signal causes the selected ROM pair to put data on the data bus Delay U1 3 and U1 4 are used to delay the DTACKL signal based on the speed of the sl...

Page 257: ...e RaMSELL signal the ROM decoder issues a chip enable CE signal to the appropriate ROM pair The CE signal enables the ROM pair to put data on the ROM data bus The ROMS E LL signal gates the data through the data bus drivers onto the system data bus and returns DTACKL data acknowledge to the system CPU Internal Signal Descriptions CE1 l through CE20l C lK ROMSE LL Chip enable 1 20 active low E nabl...

Page 258: ...E L 3562A C I RC U IT DESCRI PTIONS 8 MHz I I WRITEL I I I i I A1 A23 Valid Address I I ASL I I 1 ROMSELL CE1 L CE20L _______ _ 11 ____ I DTACKL _______ ___ 4 FIgure 6 A3a ROM TImIng DIagram I 1 I 6 35 6 36 ...

Page 259: ...WRITEL A22L l cc E Vl 8 MHz A23L ASL Inverting A1L A21 L D rivers r ...

Page 260: ... A21 I ROMSELL Address I Delay Comparator r ROM Decoders CE1 L CE20L I A1 A1 6 OEL A1 7 rr Figure 6 A3b ROM Block Diagram DTACKL ROM Data System Memory Bus DOL D1 5L Data Bus Driver Data Bus 6 37 6 38 ...

Page 261: ...into the LO s system bus interface This data contains a command byte to put the LO in the desired mode of operation the mode is determined by the instrument setup Once the LO is initialized with the mode of operation and desired frequency values the system CPU is no longer needed for the sine wave generation process 1 Jt 1 i e g li v i i g eM J ata f inG i i bin s S y stei H f IEI td iE p a H I I ...

Page 262: ...CPU W hen a trigger occu rs the phase value of the cosine is latched into the phase output l atchs The system CPU reads this value through the system bus interface and uses this i nformation for an input correction factor The self test shift registers are u sed to test the assembly During self test the system CPU reads and verifie s the values from the self test sh ift registers and the phase latc...

Page 263: ...ROM takes in 1 3 phase bits an address and outputs 1 6 amplitude bits data Interpolator and Adder The interpolator is used to increase the phase resolution of the sine ROM output and produce the data needed for a complete sine wave The interpolator ROM U1 3 uses the output from the phase accumulator to produce an interpolate value This value is added to or subtracted from the sine ROM output to pr...

Page 264: ...em CPU SYSTEM ADDRESS BUS SYSTEMA To I From System CPU BUS _ CONTROL I To I From System CPU From A1 Digital Source jYSTEM DATA BUS BFST Y 1 r 7 Phase Data M00 to M07 SYSTEM BUS INTERFACE LD0 to LD15 LD LD VALOUT ...

Page 265: ...Addresses 11 5 15 I PHASE OUTPUT LATCHS SELF TEST SH IFT REG ISTERS 1 SINE ROM Figure 6 A4 Local Oscillator Block Diagram A1 Source T INTER POLATOR AND ADDER NSYNC I To Digital Source 1 6 Timing Select Output LO OUTPUT BUFFER SINE 1 To Digital Filter COS 1 i1lO To Digital Filter l NOAT To Digital Source NLD 1 To Digital Source NDCIL 1 To Digital Source 6 43 6 44 ...

Page 266: ...e digital filter blocks where they are processed A4 I LO I sin BD I cos I A32 I Serial A34 ADC I Data BD From I ADC 1 2 I I I I A2 Sys Adr Bus CPU BD Sys Data Bus r I I I I I AS I Digital L Jo Fiit Global Bus I Local I Data V I Control Bus r Lines I I A6 I Filter I Control I Filter can pass d to RAM without filt ata ering ter it and pull it out fil later A8 RAM Figure 6 ASa System Block Diagram Re...

Page 267: ...eal From ADC Board Filter Signals From Sin LO Board cos Freq Center Freq J Figure 6 ASb Zoom Implementation Imag Filter Data Ready For Single Channel Complex FFT Yields Frequency Span Other Than 0 100 KHz W hen he processed data is ready for storage the control ler ICs req uest the digital fi lter local data bus When granted use of the bus the controller ICs transfer the data to the global data bu...

Page 268: ...band non zoom mode the control le outputs filtered data from the real filter I n zoom mode the control le outputs the real data first fol lowed by the imaginary data 0152 The control le outputs the data from the imaginary fi lter third octave 0153 The control le outputs unfiltered data Chan Overlc Dete From Data 1 ADC 1 From s in LO cos 2 LO S ign Const Sele From _ l Da t a 2 4 ADC2 LO Chan Overlc...

Page 269: ...Chan 2 Digital Filter D B r 1 Digital Filter Local Data Bus Interface Y I Local Control Data Lines 4 Bus To From A6 To From A6 Figure 6 ASc AS Block Diagram Global Global r Data Data Bus Bus I nterface Handshake I Lines Global Bus DMA Control Address Global Parallel Output Address Input Registers Bus Control V v Local Data r DMABus 1 r Interface 6 47 6 48 ...

Page 270: ... from the local data bus The information passing through these ICs consists of configuration commands from the system data bus to the digital filters and status information from the digital filters to the system data bus F I LTER CONTROL The fi lter control block controls data flow for the three digital filter modes When a filter controller IC has data ready to store in global RAM it requests the ...

Page 271: ...stem data bus interface consists of tristate transceivers connecting the system data bus and the local data bus The system CPU conf igu res and reads status from various registers in the digital f ilter assembly through this interface and the local data bus SYSTEM ADDRESS DECODE R The system address decoder i s divided between the AS and A6 boards with some of the c ircuitry appearing on each The ...

Page 272: ...ut and the NAND gates driving the read and write i nputs to the cou nter After four clock cycles of delay the proper configuration signals cause the counter to write to or read from the local data bus System L System Data Data Bus Bus Interface To CPU IRQTSL To Kybd Trigger LED Control Digital Source System System Address Address Bus Decoder Figure 6 ASd A6 Block Diagram U I Interrupt I Control Li...

Page 273: ...ly The status register is an eight l ine latch which allows the A1 CPU to read the status of the digital filter assembly The status word is latched onto the local data bus when the RD I BCSTATL signal is activated Bit 0 is a signal cal led NOTREALTIME FLG This signal activates when data can not be moved through the DFA fast enough to prevent delay of further measurements I n this case the data in ...

Page 274: ...ock is fil led Set when the parallel input data blocks have been emptied When one of these interrupt flags is set the digital filter control ler sends an interrupt lRQTSL to the A2 System CPU After receiving the interrupt the system CPU reads the I nterrupt Register Latch U302 to determ ine which signal caused the interrupt Any combination of flags may be cleared through the CLRI NTL signal and th...

Page 275: ...ransm it acknowledge Timing signal from measurement control machine to start stop control and trigger control Signal activated in the trigger LED control block each time a trigger occurs Used with TRIGGERED to select the measu rement mode If TRIGG E R E D is set and FRE ERU N is clear triggered mode is selected If FREERUN is set and TRIGG ERE D is clear freeru n mode is selected If both bits are c...

Page 276: ...er event has occu rred after being armed Write input buffer control command Clocks commands from the local data bus into the command register Write interrupt mask Used to mask interrupt flags Internal Signal Descriptions AS 2XClK l CH1A DDATA CH1AEN CH2AEN CH1 B R1 CH2BR1 CH1 B R2 CH2BR2 CH1 B R3 CH2BR3 CH1 DACK3l CH 2DACK3 l CH1 DIS1 CH2DIS1 CH1 DIS2 CH2DIS2 CH1 DIS3 CH2DIS2 CH1 DMACS CH 2DMACS T...

Page 277: ... the Digital Filter Control ler assembly used to used to sel ect the input to the d igital filters The input can be either the sine cosine data from the local oscillator or a locally generated constant CH1MEMRL CH2MEMRL Clock data through global data bus interface CH1 MEMWL CH2MEMWL CH1 0VLD CH20VLD Status lines to Fi lter Controller to indicate overload CH1 OVLD L CH2 OVLD L condition on ADC asse...

Page 278: ... reset signal Data valid strobes for mode words 1 and 2 and external parallel AID data on the data bus Data valid strobe for external parallel AID data on the data bus Signals from the paral lel input control block which control the input of data from G lobal RAM to the digital fi lters AID self test input to filter ICs LO self test input to filter ICs Write input buffer control command Clocks dat...

Page 279: ...A command stack consists of the following 32 bit command word add sub etc Number of entries in the data block which are to be operated on Constants to indicate if the data block is real or complex The beginning address of the data block in global RAM The destination address of the results Commands may be executed individually or in groups Commands in groups are executed i n series and can include ...

Page 280: ...iously specified in the command stack 1 4 The FPP fetches the next command stack 1 5 Steps 5 through 1 3 are repeated until all the command stacks are done unless the FPP is reset or an error is detected by the condition code multiplexor 1 6 The sequencer addresses the m icrocode memory for the wait command 1 7 The wait command is executed using the constant pipeline interface The FPP remains in a...

Page 281: ...it word For 32 bit floating point data the first data word contains the most significant bits of a mantissa and the second data word contains the least signifi cant bits of the mantissa and the exponent This results in a 24 bit mantissa 8 bit exponent floating point data word To start the global bus transfer the ALUs write the global RAM add ress for the data word on the B bus The bus control PROM...

Page 282: ...instruction bus by the ALUs internal instruction decoder The ALUs have a 1 6 x 24 bit RAM for storing data To load the ALUs RAM the data i n the global b u s registers i s placed on the Y bus when MAN L i s active and on the B bus when EXPL is active The A Port Address from the m icrocode memory determines the storage location of the data block add ress upper Y bus and the B Port Address deter m i...

Page 283: ...Y7 and B1 7 to B23 global bus registers CLEAR I NTE RRUPT REQU EST Clears the I nterrupt Request I RQT3L CONSTANT P I PE L I N E DATA Output signal of the B bus Y bus control register which enables the pipeline data bus onto the Y bus E NABLE A This signal from the bus control PROM selects the input to the ALUs ALUs internal RAM or Y bus E NABLE H I GH Y BUS OUT Signa from control Pl L 2 vvhich en...

Page 284: ... the Y bus MY ADDRESS Output signal of the address comparator to indicate the FPP assembly has been add ressed by the A2 System CPU OPTION C LOCK This signal clocks the cond ition code of the FPP assembly i nto the cond ition code mu ltiplexor Q BIT 0 This input to control PAL 1 determi nes whether CA1 L is low or high OUTPUT 1 The output of control PAL 1 to control PAL 2 to indicate which half of...

Page 285: ...5L 8 MHz From System CPU Clock Generator System Address Decoder and Handshake Command Pointer Registers SYSCLK 4 MHz l J CCODE f ADDFLG TBIT r 0 1 6 16 Condition Code Multi Plexer I nstruction Matching PROM MRFLG X Bus 8 23 Condition Code Pipeline D B 0 7 Y Pipeli Sequen AM 291 Data Block Address Arithmetic Logic Units ALU s AM 2903 8 23 r B Bus 0 23 ...

Page 286: ...nt Data Options A e 6 A7 FPP Block Diagram G lobal Bus Control r 0 8 0 3 rv Y Bus B Bus MRFPPL GR GWL MGFPPL GDSL Control Lines 8 Ut Global Bus 0 23 t Registers Global 0 23 Bus Registers Global j 0 1 5 Data Bus GDOL to GD15L lA G lobal Bus Register j A Global Bus B lgeL 0 j Global Global 0 1 Address Address IV Registers Bus GA1 L to GA1 6L j 6 65 6 66 ...

Page 287: ... is allowed two consecutive memory cycles if no higher priority device is requesting memory A two wire handshake coordinates memory requests and grants When a device wants memory access it first sets up valid global address and data at its output bus drivers The device then in itiates handshak ing by asserting its memory request line low When the device is ailocated a memory cycle its memory grant...

Page 288: ...ltiplexer is disabled The refresh address counter U51 1 and U51 2 is enabled The output is applied to the memory address drivers to set up the memory row to be refreshed The row address strobe signals RASU L and RASLL are enabled and a read memory operation refreshes the RAM memory row Global Bus Transceivers The global bus transceivers U609 and U61 0 are bi directional inverting buffers which tra...

Page 289: ...lock to 61 Hz U201 is clocked by this 61 Hz signal and puts out a SYNC pulse every 1 6 4 msec Each time the system CPU starts a new display frame it sets D1 5 on the system bus This signal is used to reset the d isplay refresh timer to coord inate the sync pu lses with the new frame information D ISPLAY I NTE RFAC E A1 7 One section of the display interface board buffers information and control si...

Page 290: ...he i nverse of the arbiter circuit signal YD which indicates a memory refresh grant GOO G lobal data lines between dynam ic memory and global bus through transceivers GD1 5 GSMP Global sample A 4 26 MHz clock produced by the delay line timer and used as the c lock for the synchronizing register I D lH Idle active low Ensures that global RAM does not change when there is no memory grant asserted MA...

Page 291: ...a point is required Row enable Switches the output of the address multiplexer Rest Software reset for the global RAM board originates from the system CPU Signal from global timing circuit used to generate global data strobe G DSL Output of the display refresh timer used to synchronize frame refresh approximately 61 Hz Terminate count active low I ndicates that the display word count has gone to ze...

Page 292: ... Inverting Receiver Address Multiplexer Memory Refresh Timer Refresh Address Counter Memory Address Drivers Global Timing 6 ABa Global RAM Memory Control Drivers 64K X 16 Bit Dynamic Memory Array ...

Page 293: ...lay Bus Driver Bus r Display Controller I Global I nverting Display Data Bus Bus r Receiver Display DMA I ddres Word Address Counters Bus Analog X Y Z Output Output Outputs Protection From Circuitry To Rear 1 345A Panel Display A8 Display Controller A1 7 Display Interface 6 ABb Display Controller I Interface 6 73 6 74 ...

Page 294: ... System The FFT microprocessor U1 03 is a TMS320 runn ing at 5 MHz The crystal oscillates at 20 MHz but the TMS320 divides that by four The TMS320 and its ROM U301 and U303 form a complete microprocessor system The data bus between the TMS320 and its ROM is connected to the FFT intemal data bus through a transceiver The rest of the circu itry on the board appears to this system as individual I O p...

Page 295: ...o tel l the sequencer when the TMS320 has accessed or provided data for the next I O operation The sequencer also initiates hand shaking when the FFT needs memory access S E Q U E NCE DECOD ER The sequence decoder U1 15 decodes the outputs of the I O sequencer When the TMS320 begins a new level the Fast Fourier Transform is performed in levels five of which are called butterfly routines it initial...

Page 296: ...the RAM location for input and output blocks The TMS320 sets the inputs which are written to once at the beginning of the transform The page register specifies the four most signifi cant bits of the FFT address bus dependent on whether the memory access is a read or a write state of the FFTWR signal and whether the information being accessed is window data or FFT data state of the WI NDPG L signal...

Page 297: ...ice routine reads the address bus through the address bus buffer U505 onto the internal data bus When the address is read the interru pt is cleared and the data is transferred in the appropriate direction through the system data bus If the CPU is writing to the FFT board the TMS320 reads the data registers by asserting the SDBUS I N L system data bus in signal which activates DTACKL data acknowled...

Page 298: ...loaded into the write register at the same time the GR GWL global read global write signal is set low to indicate to the memory that the data on the bus is valid Pseudo Scale ROM All data operations are done in the TMS320 microprocessor The only hardware doing math operations outside the TMS320 is the pseudo scale ROM U305 It looks at the internal data bus on each data write cycle and compares the...

Page 299: ...l data bus It d rives the LED arrays CR101 and CR102 One line is used as the start stop signal for digital signatu re analysis DSA Another line is used to clear the pseudorandom generator Internal Signal Descriptions PORT DECODER OUTPUTS SIRQSYS L Set interrupt request to system active low RI RQSYS L Reset interrupt request to system active low G DB I N L Global data bus in active low GDBOUTl Glob...

Page 300: ...select one of seven levels within the FFT process The seven levels are window five butterfly passes and if necessary deinterlace Each level processes an entire block of data i n memory The LEV signals help keep track of addressing These three lines are used to choose one of four signals used by the test bit mux These l ines are used to select one of three signals to convey information about the ma...

Page 301: ...mation or coefficient information It is not possible to write coefficient information WINDPG L Window page active low Used in conjunction with FFTWR as input to the page register See FFTWR PASSB ITO A signal ANDed with bit 0 on the FFT address bus so that it passes bit 0 when high and holds bit 0 low when low See the discussion on the address translator GDIN EMPTY G lobal data input register empty...

Page 302: ... loads data from the global data bus into the read registers It is activated when the FFT is granted memory access and G DSL global data strobe becomes active Iow Branch on I O active low A signal from the test bit mux to the TMS320 microprocessor I nterrupt request to the TMS320 microprocessor active low Board select active h igh Signal created by the identity comparator in the FFT interrupt circ...

Page 303: ...s Address 5 Bus Buffer System Data A System Data Bus _ Bus l I nterface r J IRQ4L RESETL CPU Interrupt e t B10 TMS320 LP IRQ L Jo Address Bus A ROM lS Data Bus r Port Decoder XCVR a Hardware 1V7 e_____ Control Register fl LED Keglsrer FIgure 6 A ...

Page 304: ... Board Block DIagram t Pseudorandom Number Generator PASSDONE c e TYPE 2BF I it Address Generation Butterfly See Fig 6 A9b Subroutine Address ROM I Jvt 7 G lobal 1 2 Bus Handshaking 12 Global ress Bus Address Global Address Bus Bus Interface e Global Data Bus Global Data Bus r Interface 6 85 6 86 ...

Page 305: ...c c I O Sequencer S r J Sequence Decoder ...

Page 306: ...us Handshaking Didone Counter Passdone One e c I A Butterfly Type 2BF I Type PLA c s Counter Address MUX Translator Address r FFT Address Bus Count Bus jI i c c I Counter Page s Two Register e e e 6 A9b Address Generation Block Coefficient ROM 6 87 6 88 ...

Page 307: ...hen it is inter facing with the system CPU The output port controls a BCD to decimal decoder and mu ltiplexer When a key is pressed by the operator an input l ine to the mu ltiplexer is grounded and the KEY l ine is asserted When the keyboard processor senses the asserted KEY l ine it reads the matrix counter and stores the value internal ly At the same time the keyboard processor asserts I RQ cau...

Page 308: ... TTL level low The output of the turn latch RPG1 toggles the clock of the direction latch The output of the direction latch D I R1 depends on the direction the RPG is turned After the RPG1 and DI R1 signals are sent to the keyboard processor the following occurs 1 The keyboard processor polls the RPG1 and D I R1 lines and IRQT2L is sent to the A2 System CPU 2 The system processor instructs the key...

Page 309: ...M7 The keyboard EPROM sends instructions to the keyboard processor using these lines KEYBOARD ACKNOWLEDGE Active Low Signal from the keyboard device decoder to clock DTACKL out to the A2 System CPU KEYBOARD ADDRESS STROBE Signal from the keyboard processor indicating addresses KAB to KA1 2 are val id V C V D r A D n D I I C 1 I I C L L _ _ _ L 7 L v u v u L I I I L U lIlI UUgl1 I Keyboard data lin...

Page 310: ...yboard data from the data output register is put on the system bus OUTPUT REG ISTER Active Low This signal clocks keyboard data into the data output register PORT AO to PORT A7 Port A lines are output l ines of the keyboard processor The keyboard processor uses PAO to PA6 to set up the key matrix and uses PA7 to clock I RQT2 L to the A2 System CPU ROTATION PULSE G EN E RATOR 1 When the marker RPG ...

Page 311: ... FROM 7 1 A2 SYSTEM CPU Dcf L TO 07L FROM A2 SYSTEM CPU ADDRESS L I N ES 7 1 DTACKL A2 SYSTEM CPU IRQTL ...

Page 312: ...SSOR A KA1 1 KA1 2 LED1 L DEVICE DECODER KDS LED2LJ LED S KRD interrup t r Sr 4 t OMMAND R E G I STE R ANDSHAKE NTERRUPT C I RCUIT COMMAND KACKL CLRPG L RPG C I RC U I T I RQ 4 Figure 6 A1 5 Keyboard Block Diagram DI RECTION KEYBOARD KEY SCAN MATRIX key inpu t 6 93 6 94 ...

Page 313: ...ent the power supply is tu rned on the primary capacitors and the bias power supply capacitors begin charging The supply is not switching and the entire instrument is in the reset mode The power down circuit monitors the bias supply s transformer to determ ine when the l ine voltage is at the correct level When the voltage reaches the correct level the power down circuit signals the PWM and the po...

Page 314: ...e power must be cycled for the instrument to operate When switch S1 is in the 1 1 5V position and the l ine voltage drops to less than 84 Vrms the power fail sign PWRDNL becomes active If the l ine voltage drops to less than 1 60 Vrms PWRDN L becomes active when switch S1 is in the 220V switch position This signal goes to the protection and current monitors and the PWM is shut off The power down s...

Page 315: ... POWER CONN ECTOR 1 1 5V S1 220V O N C LINE FILTER BIAS POWER SUPPLY PRIMARY RECTIFI E R 1 2V to Protection Monitor Vdc U 11 Vdc c l PR F P c r PRIM CURRI LlMI to Protection Monitor J Sy 256 kHz SMP OUT ...

Page 316: ...ransformer I L _ L 5 V Ref J C uPplY I I I 1 f1f JLf _CONTROL VOLTAG E Lj WIDTH MODULATOR 2 V 5hut down I SLOW START POWER DOWN re 6 A18 Power Supply Block Diagram AMP I CURRENT I 1 MONITOR I I I OVER 1 OTEMPL TEMPERATURE I 30V 1 5A 1 55 851 852 55 IREGULATO 2 6V from from Primary Bias Current SU r y li T I PROTECTION I f MON ITOR PWRDNL ID PWRUP 6 97 6 98 ...

Page 317: ...serial to parallel shift registers U553 and U552 The clock used to shift in the data is on pin 40 and the enable signal is on pin 27 The paral lel output is latched by U551 and U550 into the D A converter DAC U551 Source Signa DAC U551 changes the digital information originating on the digital source board into an analog signal The output is a cu rrent signal which is converted to a voltage signal...

Page 318: ...C U301 receives offset i nformation in digital format from U500 and converts it to an analog cu rrent signal The cu rrent signal is changed to a voltage signal by U300 The output of U300 is connected to the switch U1 51 This signal is opposite in polarity and half the final amplitude of the dc offset The switch is required because the DAC output signal is not exactly zero when zero offset is selec...

Page 319: ...gnal and its inverse The control lines S E LCAL and I NVCAL from U502 select one of the four signals to pass to the cal ibrator circuit and to send to the trigger board as the signal CALTRIG Pseudo random noise is not used for a CALTRIG signal but a signal from the PRN source is connected to both C2 and C3 of the CALTRIG selector U452A See table A30 2 in section VI I I for specific control informa...

Page 320: ......

Page 321: ... From Digital Source From Digital Source Serial Data Serial Data Sinewave Interface Front End Interface 3 S D D ...

Page 322: ... Front 100 KHz LPF Attenuator Panel verter Output Input Boards TP1 0 TP8 fset Offset verter Switch Signal Selection Calibrator 2 Mux Pseudo To Square Random Overload Digital Wave Noise Detection Source Source Source 6 103 6 1 04 ...

Page 323: ...external trigger EXT TRI GGER channel 1 TRIG1 channel 2 TRIG2 or trigger calibration CALTRIG The trigger select switch selects one of the input signals and passes it to a comparator The selected analog input is compared to a dc voltage from the trigger s DAC The output of the comparator is lbw as long as the analog signal is below this dc value and is high if the analog signal is above the dc valu...

Page 324: ...EXT TRIGGER TRIG 1 TRIG 2 CALTRIG CNTLD COMI W CNTCLK LDTRGL RESETL ...

Page 325: ...f V TRIGG ER SELECT TRIGGER DAC f TRIGG E R LEVEL SLOPE SELECT I I SHIFT REG ISTER Figure 6 A31 a Trigger Level Block Diagram Slope Control TRIGRO To Digital Source and Digital Filter Controller SHXS To Convert Multiplexer 6 1 07 6 108 ...

Page 326: ...reference signal s harmonics These frequencies are then put through a bandpass filter to produce an 80 kHz signal At the same time the 80 kHz signal is being produced the REF IN is divided by 1 25 The phase detector samples the 80 kHz s ignal with the RE F I N 1 25 signal to produce an er ror voltage The error voltage is amplified and passed through a switchable low pass filter to generate the con...

Page 327: ... RH r I N EXT BUFFER SAMPLE _ _ _ IN ...

Page 328: ...NG Voltage u 80 kHz 80 kHz BANDPASS FILTER Difference Frequencies SAMPLER 6 20 48 MHz Figure 6 A3 1 b Trigger Clock Block Diagram 2 4 10 10 20 48 MHz 10 24 MHz SMPOUT To Power Supply SELXS r 1 External Sample o I nternal Sample I I PLEXER I CONVERT MULTI I1 _ _ CONV TO ADC 6 111 6 1 1 2 ...

Page 329: ...rd through 200 and a balun and goes to attenuator 2 1 is on the input board This attenuator is variable in 2 dB steps from o dB to 1 2 d B It can also ground the input of the next amplifier for calibration purposes The configu ration information for th is attenuator and attenuator 3 come from serial to parallel S P shift register U203 This i nformation comes on the board from the input board and i...

Page 330: ...1 0 4 0 0 0 6 0 1 0 6 0 0 0 8 0 1 0 8 0 0 0 1 0 0 1 0 1 0 0 0 0 1 2 0 1 0 1 2 0 0 0 1 4 0 1 0 1 4 0 0 2 1 4 0 1 2 1 4 0 0 4 1 4 0 1 4 1 4 0 0 6 1 4 0 1 6 1 4 0 0 8 1 4 0 1 8 1 4 0 0 1 0 1 4 0 1 1 0 1 4 0 0 1 2 1 4 0 1 1 2 1 4 0 1 2 2 1 4 0 1 3 2 1 4 0 1 2 4 1 4 1fig im i m 1 iiiiiI 4 1 h 1 0 1 3 6 1 4 0 1 2 8 1 4 0 1 3 8 1 4 0 1 2 1 0 1 4 0 1 3 1 0 1 4 0 1 2 1 2 1 4 20 1 4 1 4 MODEL 3562A Total At...

Page 331: ...o 1 o 1 1 2 1 3 1 2 1 3 1 2 1 3 1 2 1 3 1 2 1 3 1 2 1 o 1 o 1 o 1 o 1 1 2 1 3 Atten 2 dB 6 6 8 8 1 0 1 0 1 2 1 2 2 2 4 4 6 6 8 8 1 0 1 0 1 2 4 6 6 8 8 1 0 1 0 1 2 1 2 2 2 Atten 3 dB 1 4 1 4 1 4 1 4 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 1 4 1 4 1 4 1 4 1 4 A I T Total Atten dB 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 67 68 69 68 69 22 4 0 1 3 ...

Page 332: ...hold Input vs output Digital r I t t L TRACK HOLD e conversIOn process starts w en e controller receives a start conversion signal CCONV from the trigger board The ADC board in channel two generates the control signals which coord inates the two passes and contr ls the process switches on both boards The T H OUT signal is converted to a 1 3 bit digital word by passing the signal through an 8 b it ...

Page 333: ...to send a 34 volt dc signal to the AID converter to reset it This third pass shows in figure 6 A32b as the high portion of the signal The first pass appears as the signal following a roughly sinusoidal pattern and the second pass appears as a noisy signal centered within the first pass sine wave 1 l I t l _ _ t_ _ 1 o 3RD PASS Figure 6 A32b Process switch output TP40S Table 6 A32b Process switch c...

Page 334: ...ay be diagnosed by using self tests which are activated by front panel key presses Configura tion commands and test signals are sent to the ADC board as serial data through the serial paral lel shift register U603 so the self tests also check the CNTLDAD control data path Master Slave Selection There is an ADC board in each analyzer input channel These are identical boards The digitizing process m...

Page 335: ...board and A34 analog digital converter board This signal determines which board is in control If both boards are installed A32 is in control END OF CONVERSION When both analog digital converter boards are instal led A32 s control ler tells A34 s control ler it is done with a conversion GSW PROCESS SWITCH SIGNAL LCNV Signal from the controll ing ADC control ler to the process switch on each board I...

Page 336: ...STAG ES 6 I OFFSET DAC Digital 8 Offset SHIFT 5 REG ISTERS LATCHES 1 3 6 2 Volts CONVERSI Reference DAC Voltage ANTI ALIAS TRACK 1 AND FILTER HOLD b t TRH CONV Self diagnostic Test Lines I OVE R RANGE 1 HALF RANGE COVLD L __ __ C _ I R _ C _ U _ I _ T__ _ Figure 6 A32 ...

Page 337: ...CONY I ADC from AS Digital Filter DREQL DATA CONTROLLER MISSED SAMPLE CIRCUIT OVLD MSMP TO AS DIG ITAL FILTER TO AS DIG ITAL FILTER TO AS DIG ITAL FILTER __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ H L FS C L TO AS DIG ITAL FILTER A15 KEYBOARD lalog Digital Converter Block Diagram 6 1 21 6 1 22 ...

Page 338: ...r self tests and calibration After the signal is attenuated it goes into a buffer The buffer s power supplies are bootstrapped to al low for a 20V common mode signal After the H I GH input and LOW input signals are attenuated and buffered they are subtracted using a difference amplifier The output of the difference amplifier is sent to a times three amplifier which is adjustable for gain and de of...

Page 339: ... followers The emitter follower provides the power to the buffer while the current source keeps the voltage across the zener at S 6Y above the input T h is creates a stable power supply for the buffer so it has unity gain for a wide voltage range even at high frequencies The 30V protection diodes are also bootstrapped to the power supply to avoid distortion The LOW side of the input has the same c...

Page 340: ... IN _ P _ U T__ I N PUT SWI TCH ES F BUFI ATTENUATORS X1 CHANN E L C r _ad BNC HI BC CII from Relay Drivers LOW V 2 LOW _ __ LO _ W I _ N _ PU _ T I N PUT SWITC H E S 1 BUFF ATTEN UATORS to High Input Switches A RE LAY DRIVERS Le BC CII ...

Page 341: ...T REG I STE RS e 6 A33 Input Block Diagram Voltage Reference R to Attenuator 1 ATTEN UATOR 1 from I nterface Shift Registers IN PUT TO ADC _ _ __ __ __ __ __ __ __ __ __ COVLD TO ADC ADC Control Data Word CNTLD AD TO ADC 6 1 25 6 1 26 ...

Page 342: ... VOLTS 1 5S A1 8 J1 9 1 5S A1 8 J1 1 0 Voltage output from the A1 8 Power Supply that goes to the following assembl ies HP 1 345A Display A1 Digital Source AS Digital Fi lter A2 System CPU not used 2 6 VOLTS A1 8 J1 6 Voltage output from the A18 Power Supply that goes to the termination networks on the A1 2 Mother Assembly Toltage output from the A1 8 Power Supply that goes to the following assemb...

Page 343: ...d from the 8 V output and the 1 5 V output 8 1 5 23 Vdc 8 MHz CLOCK A2 TP5 Clock from the A2 System CPU to the following assembl ies A3 Program ROM A7 Floating Point Transform Processor A8 G lobal RAM Display 1 0 24 MHz C LOCK A4 TP1 8 A1 TP4 Clock form the A31 Trigger assembly to the fol lowing assembl ies A1 Digital Source A4 Local Oscil lator A30 A32 A34 er Serial data from the A32 A34 Analog D...

Page 344: ...ram ROM Active Low Low Signal from the A6 Digital Filter Control ler to the A1 Digital Source to start a triggered measu rement process ARML stays asserted until the rising edge of BFST ADDRESS STROBE Active Low This is the system address bus strobe from the A2 System CPU assembly When the Address strobe signal is low a valid address is on the system bus ATTENTION Signal to and from the A2 System ...

Page 345: ...y filter auxiliary data block BLK2FU LL or the unfiltered data block BLK3FU LL is full the positive going transition of these signals sets the corresponding interrupt flag flip flop on the A6 D igital Filter Control ler BUFFE RED RESET Active Low This signal is from the A6 Digital Filter Control ler to the AS Digital Filter assembly It is the buffered version of the system bus line RESETL BUFFERED...

Page 346: ...or CH2 BR1 L goes low If the transfer is a real data transfer CH1 BR1 L or CH2BR1 L goes high when the AS Digital Filter gets the grant signal CH1 BG1 L or CH2BG1 L from the A6 Digital Filter Controller If the transfer is a com plex operation zoom CH1 BR1 L or CH2 BR1 L goes high after the second grant signal CHAN N E L 1 LOCAL OSCI LLATOR SELECT BITS CHAN N E L 2 LOCAL OSC I LLATOR SELECT BITS Ac...

Page 347: ...ce CONTROL DATA WORD A1 TP1 0 This is the serial com mand data word from the A1 Digital Source to the fol lowing assemblies A33 A34 A31 A30 I nput Trigger Analog Source CONTROL DATA WORD TO ADC 1 CONTROL DATA WORD TO ADC 2 These are the serial command data words from the A33 A35 I nput assembl ies to the A32 A34 Analog Digital Converters CNTL DAD1 and CNTL DAD2 are part of the data word CNTLD from...

Page 348: ... jO I N PUT OVERLOAD CHAN N E L 1 I N PUT OVERLOAD CHANNEL 2 A32 A34 TP501 Active Low The signals from the A33 A35 I nput assembl ies to the A32 A34 Analog Digital Converters ind icating the front panel input voltage to chassis grou nd is too high SYSTEM DATA BUS Active Low The system data bus is a bidirectional bus that serves as a general pu rpose data path for the fol lowing assembl ies A1 A2 A...

Page 349: ...ion D ISPLAY OUTPUT X Y Z DMADTACKL DRE L DSA SS These signals are outputs of the H P 1 34SA display Refer to the HP 1 345A operating and service manual for troubleshooting and adjust ing the display DMA DATA TRANSFER ACKNOWLEDG E Active Low This signal is from the AS Digital Filter to the A6 Digital Filter Controller When a read filter status command or a read write to a AS DMA controller registe...

Page 350: ... L signal for data transfer A1 A3 A6 A7 AB A9 A1 5 Digital Source Program RoM Digital Filter Controller Floating Point Transform Processor G lobal RAM D isplay Fast Fourier Processor Keyboard END OF CONVE RS ION A32 A34 TP605 This signal is used by the A32 ADC 1 and the A34 ADC 2 When both assemblies are installed ADC 2 tells ADC 1 when it is done with a conversion END Signal to and from the A2 Sy...

Page 351: ...o G01 5 l G LOBAL DATA BUS Active Low GOSl The global data bus provides a communication path between the following assembl ies A2 AS A7 A8 A9 A1 7 System CPU Digital Filter Floating Point Transform Processor Global RAM Display Fast Fou rier Processor Display I nterface G LOBAL DATA STROBE Active Low When a device reads A8 G lobal RAM the low to high edge of the global data strobe signal indicates ...

Page 352: ... System CPU to the A8 G lobal RAM When power is applied to the instrument or A2 S1 is activated G RAMRSTL goes low and resets the global RAM This signal is used to reset the global RAM instead of RESETL so a software reset does not reset the A8 G lobal RAM G LOBAL SAMPLE Active Low At this time this signal from the A8 G lobal RAM is not used by any assembly in the instrument PASS GAI N SWI TC H A3...

Page 353: ... 1 or A34 ADC 2 assemblies This s ignal goes h igh when the current input block of the A8 Global RAM data is received by the AS Digital Filter The positive transition of this signal sets the correspond ing interru pt flag on the A6 Digital Fi lter Control ler CHAN N E L 1 ANALOG OUT CHAN N E L 2 ANALOG OUT A33 A3S TP400 These signals are the conditioned front panel input signals from the A33 A3S I...

Page 354: ...lso goes to the A32 ADC 1 assembly s AID converter le LOCAL DATA BUS These bidirectional data l ines are used by the AS Digital Filter and the A6 Digital Filter Controller During a AS Digital Filter read write operation these data l ines are the inverted version of the system data bus LOAD CHAN N E L 1 LOAD CHANNE L 2 Active Low Signal from the A1 Digital Source that latches command data word G JT...

Page 355: ...l RAM responds to bus requests MRDF1 L and MRDF2L by assertion of MG DF1 L or MG DF2L The two memory grant signals are asserted for about 41 0 ns The global RAM expects val id data to be on the bus within 80 ns after the memory grant is given FFT MEMORY GRANT Active Low A9 TP3 After the A9 FFT asserts the memory request line the AB Global RAM returns a memory grant The memory grant signal clears t...

Page 356: ...al when the A2 System CPU is addressing AS Digital Filter MY ADDRESS is used by the AS Digital Filter for command decod ing CH I RP C LOCK A4 TP1 9 The A1 Digital Source sends this signal to the A4 Local Oscillator at the beginning of chirp to reset the A4 Local Oscillator to the initial frequency of the chirp and to zero the phase This signal is present when other modes are used but the A4 Local ...

Page 357: ...ey are latched by the AS Digital Fi lter and can be read by the A2 System CPU as part of the digital filter status word POWER DOWN Active Low A1 8 1 1 4 A2 1 6 Signal from the A1 8 Power Supply to the A30 Analog Source and the A2 System CPU When this signal is active a power loss is occurring POWER UP A18 1 1 5 A2 1 5 When a power failure has occurred the instrument is in the reset mode until the ...

Page 358: ...gital Sour ce assembly saying a sample has been taken SIGNAL GROUND A33 A3S 300 2 A1 2 Mother Assembly grou nd connected to all the assembl ies S I N E A4 TP23 This is a digital signal from the A4 Local Oscillator to the AS Digital Fi lter When in a frequency shifting mode this signal represents a sine signal When in the real mode S I N E corresponds to 1 jO SAMPLE OUT A1 8 1 1 2 The 256 kHz clock...

Page 359: ...al oscillator and digital filter control ler to in itiate inputting serial sine cosine data into the digital filter When the LO receives SYNC2 it sends a complex value to the AS Digital Filter and a real value to the A1 Digital Source ANALOG PULSE A1 J10 This signal goes to the user output on the rear panel I t comes from the A1 Digital Source SYNC OUT is high when burst is on and low when burst i...

Page 360: ... from ADC 2 controls the track and hold switch on ADC 1 ANALOG TRIGG ER CHAN N E L 1 ANALOG TRIGG ER CHAN N E L 2 A32 A34 TP303 Conditioned analog signal from A32 A34 Analog Digital Converters to the A31 Trigger assembly TRI G G E R This signal is from the A6 Digital Filter Controller to the A1 5 Keyboard TRIGGER controls the front panel trigger LED as fol lows Measurement Mode Free run nme Trigge...

Page 361: ...A1 A4 A6 A7 AB A9 Digital Source Local Oscillator Digital Filter Controller Floating Point Transform Processor Global RAM Display Fast Fourier Processor VIOL is also used by devices in the A2 System CPU assembly VALI D MEMORY ADDRESS Active Low Signal from the A2 System CPU to the A4 Local Oscillator indicating the beginning of a synchronous bus transfer After receivi ng the val id peripheral addr...

Page 362: ...iagnostic Descriptions Self Calibration Tables FAU LT I SOLATION Page 7 1 7 3 7 3 7 3 7 4 7 8 7 1 8 7 25 7 32 7 34 7 38 7 43 7 44 7 53 7 54 7 55 7 58 7 67 N umber Title Page 7 1 Power Supply Nominal Values 7 4 7 2 Clocks 7 7 7 3 LEDs Pass Sequence 7 9 7 4 Power Up Test Codes 7 1 5 7 1 6 7 5 TEST ALL Results 7 20 f ii iii J 6 j I l gtglo _ c L f 7 8 Source Data 7 33 7 9 Burst Mode S ignals 7 34 7 1...

Page 363: ...al RAM Test Passes Display Active TEST ALL Passes G lobal RAM Test Passes Sine Wave SYNC2 Test Sine Wave Burst Chirp Triggered Sine Wave S PCL FCTN Key Map Test Log Exam ple Power Up Sequence Self Test Sequence T EST ALL Sequence Cali b ration Curves MOD E L 3562A Page 7 6 7 1 0 7 1 2 7 1 9 7 23 7 29 7 31 7 34 7 40 7 53 7 54 7 55 7 59 7 61 7 63 7 69 ...

Page 364: ... ROM DEAD go to paragraph 7 5 I nitial Conditions Test If there is no display incorrect display or the instrument does not respond when a key is pressed go to paragraph 7 5 I n itial Conditions Test For chirp and noise source failures go to paragraph 7 9 Sou rce Fai lures For trigger failures go to paragraph 7 1 1 Isolating Trigger Failures For H P I B failures go to paragraph 8 6 A 2 A 22 System ...

Page 365: ...divide the circuit under test in half half splitting 7 If the name of a nonnumerical key or E NTRY Not E nabled appears in the lower left of the display immed iately after the power up routine there may be a stuck key or shorted trace on the keyboard go to 8 1 5 8 Do not remove any assembly from the instrument with the power on There are several sensitive components in the instrument that may be d...

Page 366: ...ty symbol table in the preface of this manual I WARNING I Servi e procedures described in this section are performed with the protective covers removed and power applied Hazardous voltage and energy available at man y points can if contacted result in personal injury CAUTION Do not insert or remove any circuit board in the HP 3562A with the line power turned on Power transients caused by insertion...

Page 367: ...30V 30V 1 5A 1 5A 5 FNTEND 2 6V 851 852 1 55 1 55 OTEMPL PWRDNL PWRUP Table 1 1 Power Supply Nominal Values Return Location is A1 8 TP1 3 Output Nominal location Voltage A1 2 J1 6 1 5V A1 2 W1 3 1 30V A1 2 W1 3 2 30V A1 2 W1 3 3 1 5V A1 2 W1 3 4 1 5V A1 2 W13 5 5V A1 2 W1 3 6 2 6V A1 2 W1 3 7 8V Ai 2 W1 3 8 8V A1 2 W1 3 9 15V A1 2 W1 3 10 1 5V A1 2 W1 3 1 2 A1 2 W1 3 1 3 A1 2 W1 3 1 4 _ Voltage To...

Page 368: ...ard cycle the 5V power supply off then on 5 The keyboard shou ld respond as follows when it is reset a Beeps the beeper and flashes all the LEDs three times except CR12 Triggering CR1 7 Half Range and CR1 9 Half Range These LEDs will flash on and stay on since they are controlled by other assemblies b Beeps the beeper and then lights the LEDs one at a time in a pattern from left to right top to bo...

Page 369: ...hield to the test T position with the power ON 3 The pattern displayed should be the same as shown in figure 7 1 The main lines should all connect as shown and the lines in the lower right corner should be parallel If this pattern is not displayed start trou bleshooting with the HP 1 345A Display go to 8 1 2 4 Set jumper A1 7 W1 to the normal N position ...

Page 370: ...e incorrect go to Section VI I I 3562A TOP VI EW COVER REMOVED A1 TP4 A2 TP5 A31 TP1 0 Test location A31 TP1 0 A1 TP4 A1TPS I i FRONT Table 7 2 Clocks Waveform Probable Cause Signal Name Number of Failure 20 48 MHz 1 A31 Trigger 10 24 MHz 2 A31 Trigger 8 MHz 3 A2 Svstem C PLJ E If the fau lt has not been fou nd go to paragraph 7 6 Power Up Tests Go To 8 1 8 8 1 8 8 6 s z i 7 7 ...

Page 371: ...essages The instrument performs a calibration if the power up tests pass Power up test fai lures may be caused by one of the following conditions 1 A core assembly is defective A2 A3 A8 2 An assembly on the system bus or global bus is defective causing a bus fai lure 3 The A1 5 Keyboard system bus interface circu its are defective This may be the case when the display is normal after power up but ...

Page 372: ...ed on the A2 Test LEDs b Another Global RAM test pass eiror code is displayed and the sequence stops 5 If the LEDs pass sequence does not occur A2 DS1 is on or the instrument does not display the special function menu when SPCL FCTN is pressed go to part C 6 If the LEDs pass sequence occurs and the instrument responds when SPC L FCTN is pressed the special fu nction menu is displayed but the displ...

Page 373: ...h the A8 Global RAM go to 8 1 1 3 5 6 2 S e r v i c e T e s t s G c b a Ram P a s s a a Figure 7 2 Global RAM test passes 4 Press the line switch off 5 Repl ace the A7 FPP assembly 6 Press the line switch on and the H P 3562A keys as follows FerN SEKV TC TEST T E ST PROC TEST FPP FPP FUNCTION If this test fails start troubleshooting with the A7 FPP go to 8 1 0 7 Press the line switch off 8 Replace...

Page 374: ... LTE R TEST If this test fails start troubleshooting with the AS DGTL FLTR go to 8 9 13 If the cause of the failure has not been found go to paragraph 7 10 Control Line Test C Perform this procedure steps 1 through 20 if the LEDs pass sequence does not occu r A2 DS1 is on or the instrument does not display the special function menu when SPCL FCTN is pressed 1 Press the line switch off 2 Re m m R i...

Page 375: ...bal RAM 1 2 Press the l ine switch on The G l obal RAM and Global Bus tests are now performed The LEDs pass sequence shou ld now occu r it takes about 40s to complete and A2 DS1 shou ld be off If the LEDs pass sequence does not occur go to part E 1 3 The display should now appear as shown in figure 7 3 If the display is defective the probable cause of the fail u re is the A8 Global RAM or A1 7 Dis...

Page 376: ...oard or A1 7 Display I nterface is probably defective If possible press the keys as fol l ows SPCL FCTN NOTE If the displa y is blank or garbled the soft key menus may be unreadable The number of the soft key 51 through 58 from top to bottom for this procedure appears in parentheses after the soft key name SERVIC TEST 52 TEST PROC 53 RETURN 58 TEST TEST K EYBD 54 MEMORY 52 G LOBAL RAM 51 18 The A1...

Page 377: ...beginning of this section for he description of the power up test sequence The table lists the tests in the order they are run The A2 Test LEDs Hex code is l isted on the vertical axis of the table The assembl ies and subblocks tested or used by the power up tests are l isted on the horizontal axis of the table There are two symbols used in table 7 4 0 and X When the symbol 0 is used in the table ...

Page 378: ...ine 01 to 04 2 05 to 06 3 07 to OB 1 OC to OF 6 1 0 to 1C 4 1 D 1 1 E 7 1 F 21 20 to 33 34 to 3F 12 1 40 to 53 1 3 54 to 5 9 1 SA 9 5 B 1 0 5 C 1 1 5 D to SF 1 60 to 73 1 4 74 to 79 7A 1 0 7 B 9 7C 11 7D to 7F 80 81 23 82 24 83 25 84 to 86 1 5 87 1 7 88 1 8 89 1 9 8A to 8C 1 6 8D 20 8E to 8F 1 90 to 9F 26 AO to AF 27 BO 1 B1 8 B2 to B4 1 B5 22 B6 30 CO to CF 5 DO to DF 28 EO to EF 29 FO to FF Th t...

Page 379: ...M I nsta l led 0 0 0 0 0 0 0 0 7A Program ROM fai lure low byte 0 0 0 0 0 0 0 X 7B Program ROM fai lure h i gh byte 0 0 0 0 0 0 0 X X 7C Program ROM fai lure both bytes 0 0 0 0 0 0 0 X X X to 33 Program ROM ch ip f a i lure high byte 0 0 0 0 0 0 0 0 X to 53 Program ROM chip fai lure low byte 0 0 0 0 0 0 0 0 X o 73 Program ROM chip f a i lure both bytes 0 0 0 0 0 0 0 0 X X o 66 Program ROM fai lure...

Page 380: ...al RAM test 5 Press the l ine switch on The LEDs sequence shou ld stop on Hex B5 for about 1 3 minutes and then display H ex AF 6 If the pass error code is still 9 N start troubleshooting with the A2 System CPU go to 8 6 7 Perform steps a through c for each of the assemblies Replace the assemb lies in the following order A8 Global RAM Display A1 7 Display I nterface A9 FFT A7 FPP A5 Digital Fi lte...

Page 381: ...ssembl ies can be done individually to help isolate the fail ure Use table 7 6 as a reference when running any of the service tests When a test passes the assemblies and subblocks exercised are most likely operating correctly The Test All feature does not isolate failures on the following assembl ies Core Assemblies A32 Trigger A1 5 Keyboard A1 8 Power Supply A1 2 Mother Board A1 7 Display Interfa...

Page 382: ...s about two m inutes to complete If there is a failure it may take three minutes to complete The test log is d isplayed when the self tests are completed 5 Refer to figure 7 4 to verify the normal Test All resu lt 6 Use table 7 5 after running the Test All diagnostic 3 5 6 2 S e r v i c e F l o t 1 n g P o 1 n t Pr o e B s s o r FFT P r O C B s s o r G l o b a l R a m Zoom T e s t C a 1 1 b r a t ...

Page 383: ...il ures 7 9 Source Failures 8 1 7 A30 Analog Source 7 8 part C AS A6 D igital Filter Check 7 8 Isolating Front End Failures Use table 7 6 to help determine the fai l u re after running the Test A l l diagnostic or any i nd ividual self tests The table I ists the self tests in the order the Test All diagnostic executes them A pass message indicates the assemblies and subblocks tested are probably o...

Page 384: ...r face b it ital Source Se l f Test ital Soul ce Main Test Olt ital SiJurce Self Test 1 messages ADC Chann e l 2 message s I LO messages DFA Funct i onal Channel 1 DFA Functional Channel 2 DFA Channel 1 Rea l F i l ter DFA Chann e l 1 Imaginary F i l ter DFA Channel 2 Rea l Fi lter DFA Channel 2 Imaginary Fi lter DMA messages DFA Fi lter Bus 1 b it DFA Fi lter Bus 2 b it Table 7 6 TEST ALL Message...

Page 385: ...0 000 0 000 0 000 000 X 0000X 00000 0000X X X00 X 00 0000 00000 0000 0000 X XX X X X0 00 X0 00 00 0 0 I I AB Digital F i lter Control ler A5 SYNC 2 A5 AB Digita l Fi lter Local Bus A5 Digital Fi lter Channel 1 A5 Digital Fi lter Channe l 2 A5 DMA Contr o l ler 1 1 Ai8 I i5A Ai8 30V A18 5 Front End A33 Input Channel 1 A35 Input Channel 2 B EE bE B gI BE 0 00 000 0 0X A33 Channel 1 Interface Sh ift ...

Page 386: ... Remove the following assemblies AS Digital Filter A7 FPP A9 FFT 3 Press the l ine switch on and the H P 3562A keys as fol lows SPCL FCTN SERVIC TEST TEST MEMORY G LOBAL RAM If test fails or the display does not appear as in figure 7 5 start troubleshooting with the A8 G lobal RAM go to 8 1 1 3 5 6 2 G J c b a J Ram Figure 7 5 Global RAM Test Passes S e r v i c e T e s t s P a s s e s 7 23 ...

Page 387: ...SPCL FCTN SERVIC TEST TEST PROC TEST FFT FFT FU NCTN If this test fails start troubleshooting with the A9 FFT go to 8 1 3 10 Press the l ine switch off 11 Replace the AS DGTL FLTR assembly 1 2 Press the l ine switch on and the H P 3562A keys as fol lows F I N SERVIC TEST TEST PROC TEST DFA F I LTER TEST If this test fails start troubleshooting with the AS DGTL FLTR go to 8 9 1 3 If the display is ...

Page 388: ...put Channel 1 A34 Analog Digital Converter Channel 2 A35 Input Channel 2 NOTE For some failures it takes up to three min utes to complete a test If a test takes more than five minutes to terminate the test log is displa yed the test has failed A Signal Check J nr _ 1 Press the l ine switch off 2 Remove the top cover 3 Press the l ine switch on 4 After the power u p tests are comp leted use a scope...

Page 389: ...to view CNTCLK A1 TP1 1 CNTCLK 4 A1 Digital Sou rce Press A2 5 1 to view the STIM waveform ST IM is disabled when calibration is done A30 TP8 STIM 8 5 Press the HP 3562A keys as fol lows SPC L FCTN SERVIC TEST LOOP ON TEST SOURCE 1 Press the HP 3562A keys as fol lows SPCL FCTN S E RVIC TEST TEST SOURCE A30 Analog Source FR E N D i NTFCE LO FUNCTN Go To 8 1 8 8 1 9 8 9 7 8 part G 8 8 8 5 8 1 7 2 If...

Page 390: ...th the A5 Digital Filter and A6 Digital Fi lter Controller go to 8 9 6 If this test passes the AS Digital Filter and A6 Digital Fi lter Control ler assemblies are probably operating correctly Replace all assemblies in their card nests 7 Press the H P 3562A keys as fol lows SPCL FCTN SERVIC TEST TEST I N PUT ADC D IGTAL 8 If the ADC Gate Array test passes the data path from the ADC to the digital f...

Page 391: ...e If the digital source check passes go to part E EXCEPTION NOTE If the following is occurring a Result of TEST ALL is Floating Point Processor FFT Processor Digital Source FIE Interface Digital Source Main Test Digital Source Counters Global RAM ADC Channel 1 Gate Array ADC Channel 2 Gate Array Source Test Cb io o Inpul Operafion ca l1bralltrn LO Functional Test DFA Filtered Chan Interrupt DFA Un...

Page 392: ...OURCE LEVE L 5 V FIXED S I N E 1 kHz 3 Refer to figure 7 6 to verify the correct resu lt 0 00000 HC 2 50000 lISec f f A A I I I I 1 1 J J V V V Ch 1 2 000 valts dlv Offset T1IIIII181 500 UHc dlv DIII y 5 00000 IlleC l 1 I 1 J V V 0 000 valts 2 50000 lISec Figure 7 6 Sine Wave 4 If this test passes the A4 Local Oscillator the A1 Digital Source and the A30 Analog Source are probably operating correc...

Page 393: ...ies are probably operating correctly 3 Press the l ine switch off 4 Exchange A32 ADC1 with A32 ADC2 5 Press the l i ne switch on and repeat step 1 6 if the same channel fails as fai led before the exchange start troubieshooting with the input assembly for that channel go to 8 20 the ADC assembly for 8 If both channels failed before the exchange and also after the exchange the A33 A3S I nput and A3...

Page 394: ...erify COS at A4 TP24 Waveform 7 If this signal is not correct start troubleshooting with the A4 LO go to 8 8 7 Connect the scope to the source output on the front panel Set the scope as fol lows C H1 V Div Coupling Time Div Trigger 2 V Div dc 500 s Div C H1 8 Refer to figure 7 7 to verify the correct resu It 0 00000 sec 2 50000 Eec f f l I I I CC I I v v Ill 1 2 000 valts dlv T1IeII18e 500 usec dl...

Page 395: ...be caused by the A1 Digital Source the A4 Local Oscillator or the A30 Analog Source Follow the Source Failures procedu re starting with part A to isolate the defective assembly A Start 1 Ifall the source functions are operating except the random noise and burst random start troubleshooting with the A1 Digital Source go to 8 5 2 If a l l the source functions are operating except burst random period...

Page 396: ...cation Signal In Out Number of Failure A4 TP24 COS A4 Out 6 A4 Local Oscill ator A4 TP1 6 N DAT A4 Out 9 A4 Local Osci l lator A4 TP1 7 N LD A4 Out 1 1 A4 Local Osc i l lator A4 TP1 4 NDCK A4 Out 1 1 A4 Local Oscillator c If part B passed start troubleshooting with the A30 Analog Source go to 8 1 7 D Burst Failures 1 Press the l i ne switch off 2 Place the A1 Digital Source on the 03562 66540 exte...

Page 397: ... DACDAT A1 1 5 BURSTEN Tabl 7 9 Burst Mode SIgnals Waveform In Out Number A1 0ut 1 3 A4 Out 1 3 A1 0ut A1 0ut NOTE Probable Cause of Failure A1 Digital Source A4 Local Oscillator A1 D igital Source A1 Digital Source If NCLK fails NSYNC also fails Start troubleshooting with the A 1 Digital Source go to 8 5 7 If the signals in table 7 9 are correct start trou bleshooting with the A30 Analog Sou rce ...

Page 398: ...SOO 3 A2 USOO 1 3 Table 7 1 0 Control Lines Set 1 Probable Causes Signal In Out of Failure IRQT4L A9 Out A2 CPU A9 FFT I RQTSL A6 Out A2 CPU A6 D FLTR CONT I RQT6L AB Out A2 CPU AB RAM I RQT3L A7 Out A2 CPU A7 FPP Press any key to toggle KYBRDL A2 U604 3 KY BRDL A2 Out A2 CPU A1 S K EYBD A2 U604 S ASL A2 Out Any assembly on the system bus A2 U604 7 WRITEL A2 Out A2 CPU A1 DGTL SCE f 2 i O iI I fo ...

Page 399: ... failing control line in table 7 1 0 is now toggling or TTL level high start troubleshooting with this assembly go to Section VI I I 5 Press the line switch off 6 Replace the assembly c Perform steps 1 through 6 as follows 1 Press the l ine switch off 2 Replace the A2 System CPU in its card nest Place the AB G lobal RAM on the 03562 66540 extender board 3 Press the l ine switch on 4 After the powe...

Page 400: ...the global bus A2 CPU AS DGTL FlTR A7 FPP A8 RAM A9 FFT A1 7 DSPl A8 RAM A1 7 DSPl A8 RAM A7 FPP A8 RAM AS DGTl FlTR A8 RAM AS DGTl FlTR A8 RAM A9 FFT A8 RAM AS DGTl FlTR A8 RAM A9 FFT A8 RAM AS DGTl FlTR A8 RAM A7 FPP A8 RAM A1 7 DSPl A8 RAM A1 7 DSPl D Perform steps 1 through 6 for each of the following assembl ies A2 System CPU AS Digital Filter A7 FPP i J f 7 A F lb ro y I 1 e I a ep e 1 Press...

Page 401: ...ITEL A6 Out A6 U304 9 BUDSL A6 Out 5 lf any of the lines are not toggling start troubleshooting with the A6 Digital Filter Control ler go to 8 9 6 Replace the A6 Digital Filter Control ler in its card nest 7 1 1 ISOLATING TRIGGER FAILURES This procedure assumes the instrument operates correctly in the free run mode but does not operate correctly in the trigger mode Follow this procedure starting w...

Page 402: ...9 FFT A8 US09 7 MGDF2L A8 Out A8 RAM AS DGTL FLTR A8 US09 1 2 MGFFTL A8 Out A8 RAM A9 FFT A8 US09 14 MGDF1 L A8 Out A8 RAM AS DGTL FLTR A8 US09 1 6 MGFPPL AB Out A8 RAM A7 FPP A8 U301 8 B2G DSL A8 Out A8 RAM A1 7 DSPL A8 U406 8 DAVL A8 Out A8 RAM A1 7 DSPL o Perform steps 1 through 6 for each of the following assemblies A2 System CPU AS Digital Filter f F A 7 FP P _ _ lspla VTnterface 1 Press the ...

Page 403: ...3 Test Location Signal I n Out A6 U304 6 BLDSL A6 Out A6 U304 7 BWRITEL A6 Out A6 U304 9 BUDSL A6 Out S lf any ofthe lines are nottoggling starttroubleshooting withtheA6 Digital Filter Controller go to 8 9 6 Replace the A6 Digital Filter Controller in its card nest 7 1 1 ISOLATING TRIGGER FAILURES This procedure assumes the instrumentoperates correctly in the free run mode but does not operate cor...

Page 404: ... the A1 Digital Source go to 8 5 7 If the trigger operates correctly except in remote H P IS trigger mode and the A1 Digital Source self tests passed start troubleshooting with the A2 System C P U go to 8 6 B Use a SNC Tee to connect the front panel Source output to channel 1 and channel 2 Press the H P 3562A keys as fol lows SOU RCE SOURCE SE LECT TRIG L EVEL 5 V FIXED S I N E 1 25 Hz CHAN 1 I NP...

Page 405: ...steps 1 through 5 as follows 1 Press the line switch off 2 Put A32 ADC 1 on the 03562 66541 extender board 3 Press the line switch on 4 Repeat part B 5 Use a scope to verify the signals in table 7 1 3 are operating correctiy Table 7 1 3 Trtgaer Slanal rh r it 0 _ _ u m v cr _ m _ 7 O _ Location Signal InlOut A32 TP303 TRIG1 A32 Out A31 TP3 TRI GRO A31 Out Wav eform Number 1 5 1 5 _ c Prol able Cau...

Page 406: ...Probable Cause of Failure A34 ADC 2 go to 8 1 9 A31 Trigger go to 8 1 8 2 Put A30 Analog Source on the 03562 66541 extender board 3 Press the line switch on 4 Use a scopetoverify the signals in table 7 15 are operating correctly Press A2 S1 resetswitch onA2CPU toviewthe STIM andCALTRIGwaveforms these signals are disabled when calibration is finished Table 7 1 5 Trigger Signal Check 3 Press A2 51 t...

Page 407: ...e A6 Digital Filter Controller go to 8 9 1 1 If the instrument still does not trigger start troubleshooting with the A1 Digital Source go to 8 5 7 1 2 LOOP MODE AND INTERMITTENT FAILURES Loop mode is used for some signature analysis tests andtofind intermittentfailures Many intermittentfailures can be isolated by iunningthe self tests in this mode When the ioop mode is activated the instrument con...

Page 408: ...ubleshooting Hints 1 Common causes of intermittent failures are Cold solder joints Loose cables ICs loose in sockets Loose screws on power supply An assembly partially out of its card nest 2 An intermittentfailure in the instrument can be caused by an assembly s bottom connector that attaches the assembly to the A12 Mother Board Check for loose pins on the connector 3 Ifthe instrument intermittent...

Page 409: ...sonal injury Table 7 1 7 Instrument Waveforms All jumpers should be in normal position Probe 10 1 Important Setup Parameters Waveform C H I CPLG DC 20 48 MHz Time CH I 1 12121 mV O l v Connect CH1 to A31 TP1 0 Pulse shape rb r rh I I r I Osci lloscope OVdc II I J I I CH1 Y Diy 1 00 mY DiY CH1 Coupling dc Time DiY 20 ns Diy Trigger CH1 10 24 MHz Time Connect CH1 to A1 TP4 Pulse shape Ro _ OVdc CH1 ...

Page 410: ...dwidth Lim it ON CH1 V Diy 1 00 mV Div CH1 Coupling dc MT CH l Time Div 50 ns Div M a l n 5121 n s D i v Trigger CH1 3 Press the keys as follows to view CNTCLK SPC L FCTN SERVIC TEST LOOP ON TEST SOURCE FR E N D I NTFC E CNTCLK Time Connect CH1 to A1 TP1 1 1 1 Oscilloscope Bandwidth Lim it ON CH1 V DiY 1 00 mV Div I OVdc Time Div 10 fl s Div Trigger CH1 4 Press A2 S1 reset switch on A2 CPU after v...

Page 411: ... V Diy 200 mV Diy CH1 Coupling dc CH2 Coupling dc Time Diy 1 s DiY Trigger CH1 SYNC2 and COS Time relationship Connect CH1 to A4 TP8 Connect CH2 to A4 TP24 Pu lse shapes Oscilloscope Waveform C H l CPLG DC CH2 CPLG DC C H L 2210 mV D f v CH2 2 0 21 mV O r v J J r OVdc L J l J U OVdc I M T CH l M a i n 1 u s D I Y 5 QVd Ill I I 1 I I I CH1 V Diy 200 mV Diy OVrl lJJIIJ LIJLLLI CH2 V Diy 100 mV Diy C...

Page 412: ...ST I M STIM Connect CH1 to A30 TP8 Oscil loscope Bandwidth Lim it CH1 Y Div CH1 Coupling Time Div Trigger ISD and bU o ON 1 0 mY Diy dc 5 JLs Div C H1 Connect CH1 to A4 TP1 6 Connect CH2 to A4 TP1 7 Oscilloscope CH1 Y Div 1 00 mY Diy CH2 Y Div 200 mY Diy CH1 Coupling dc CH1 Coupling dc Time Div 500 ns Div Trigger C H1 Time Pulse shape Time Pu lse shape Ampl itude _ TAmE rel ationship Waveform OVdc...

Page 413: ...lloscope OVdc Waveform CH I CPLG DC C H l 1 0121 mV D l v I 1 M T CH2 Ma 1 n I u s D i Y 1 0 C H I CPLG DC CH I 200 mV O l v r 1 1 I l I I CH2 C P L G D C CH2 2 210 m V 0 1 V I I CH2 C P L G D C H2 2 e 0 m D v I l CH1 V Diy 200 mV DiY CH2 V Diy 200 mV DiY CH1 Coupling dc OVdc CH2 Coupling dc Time DiY 1 p s DiY Trigger CH1 Set AB 3 in test T position to view Display Refresh Display Refresh _ 000 r ...

Page 414: ...701 3 l OVdc Oscilloscope CH1 V Diy 200 mV Diy 1 CH2 V Diy 200 mV Diy l l CH1 Coupling dc OVdc CH2 Coupling dc MT CH l Time Diy 2 ms Diy M a i n 2 0 m s D l v Trigger CH1 1 3 Refer to paragraph 7 1 1 for the HP 3562A input and key presses to yiew TRIG I N and TRIGRO TR G I N and TRIGRO Time Relationship CH I CPLG DC CH2 CPLG DC CH l 1 00 mV O l v CH2 2 0 0 mV O l v Connect CH1 to A31 TP1 Connect C...

Page 415: ...scope Bandwidth Limit ON I CH1 V Diy 1 00 mV Div OVdc I CH2 V Diy 200 mV Div CH1 Coupling dc CH2 Coupling dc MT CH2 M a I n 1 m s O l v Time Div 1 ms DiY Trigger CH2 1 5 Refer to paragraph 7 1 1 for the H P3562A input and key presses to view TRIG2 and TRI GRO TRIG2 and TRIGRO Connect CH1 to A34 TP303 Connect CH2 to A31 TP3 Oscilloscope Bandwidth Limit ON CH1 V Diy 100 mV Div CH2 V Diy 200 mV Div e...

Page 416: ...ALTRIG STlM and CALTRIG Time CH l C P L G D C C H 2 C P L G D C Relationship CH I l e m V D l v C H 2 2 00 m V D i v Connect CH1 to A30 TP8 Connect CH2 to A30 30 1 9 Pu lse shape OVdc Oscilloscope r Bandwidth Lim it ON CH1 V Diy 10 mV D iv l r l r CH2 V Diy 200 mV Div OVdc I I I I CH1 Coupling dc C H2 Coupling dc M T CH l M a i n 5 u s D i Y T ime Div 5 s Div Trigger CH1 1 7 7 52 ...

Page 417: ...of soft keys or are used for other purposes such as adjustments and signature analysis SPCL1 FCTN SELF D TEST SERVIC D TEST TIME D H M S DATE D M D Y BEEPER D ON OFF SOURCE D PROTCT D PwrSRQ D ON OFF Figure 7 1 0 SPCL FCTN Key Map T l D TEST MEMORY TEST D PROC TEST SOURCE TEST INPUT TEST RESULT LOOP D ON OFF RETURN D TEST D LOG FAULT D LOG D CLEAR D TEST D CLEAR D FAULT D FAULT D FR END D AD UST A...

Page 418: ...D RETURN TEST FPP TEST D FFT TEST D DFA TEST D KEYBD TEST CPU D RETURN HP IB FUNCTN HP IB D DIAG HP IB D CONNEC D D D D RETURN FPP FUNCTN FFT D FUNCTN COMANO POINTR DFA O FFT BLOCK FUNCTN STATUS SET FILTER D FFT ALU TEST INTRPT TEST A LOCAL D 1 FFT O ALU BUS RAM TEST B DMA D J FFT D RESET BUS ROM FPP FILTER D I FFT D JUMPER BUS INTFCE ECHO I DFA D D RETURN PATT 1 DFA D R9TURN D PATT 2 RETURN I ...

Page 419: ... e T e s t s F l o a t i n g P o i n t Pr o c e s s o r FFT Pr o c e s s o r G l o b a l R a m ADC C h a nn e l 2 G a t e Ar r a y TEST MESSAGES A D C C h a n n e l 1 Lo g i c ADC C h a n n e l 1 Pos Ov e r f l o w ADC Ch a n n e l 1 N e g Ov e r f l o w TEST NAME ADC Gate Array Sou r c e Te s t C h a n 1 J n p u t Op e r a t i o n C h a n 2 J n p u t O p e r a t i o n C h a n 1 J n p u t 0 i s t ...

Page 420: ...owever a failure on any assembly may cause a fault log entry Use the fault log as a supplement to the fault isolation procedure To read the test log press the keys as follows SPCl FCTN SERVICE TEST TEST RESULT FAULT LOG Fault log messages accumulate in the fault log until the log is cleared Use table 7 18 to interpret fault log messages NOTE Using beeper commands other than those specified in this...

Page 421: ... 8F O FFFF81 AF OFFFF81 CE I Table 7 1 8 System CPU Address Map Description Fault Assembly Generating Message Mqnitor ROM A2 Program RAM A2 Data RAM AB Program ROM A3 H P I B A2 Program mable A2 Timer Display AB Keyboard A1 S FPP A7 I BC A6 Front E nd A1 CONA Timeout Trig Phase Error LO A4 Le Oscil FFT A9 Cal Failure MODEL 3562A Possible Assemblies Failing A2 A2 A2 AB A2 A3 A2 A22 A2 A2 AB A1 7 A2...

Page 422: ... descriptionofthetest result messages Foradetailed explanation of test result messages refer to the troubleshooting paragraph forthe assembly failing A Power Up Tests The power up tests consist of two sets of tests low level and high level The low level tests exercise theA2 System CPU the A3 Program ROM theA8 Global RAM the global bus and the system bus Fault and pass codes for these assemblies ar...

Page 423: ...ent Operational NO NO NO NO FIgure 7 1 2 Power up Sequence AIi Core Tests Pass STOP Test Code on Test LEDs Display Test Log STOP Test Code on Test LEDs Display Test Log STOP Enter faiiures in Test Log MODEL 3562A CORE TEST SEQUENCE 7 59 ...

Page 424: ...ormation on how to use the service test soft keys to isolate a failure SE LF TEST The SELF TEST key invokes a sequence of self tests thatthoroughly exercises the digital and analog hardware of the instrument This test is designed to be used by the user to determine if the instrument is functioning correctly If this self test sequence fails the failure is entered in the test log and SelfTest Fails ...

Page 425: ...L_ FAULT ISOLATION Instrument Operational Figure 7 1 3 SELF TEST Sequence MODEL 3562A STOP Enter failure in r t be 7 61 ...

Page 426: ...ughly exercises the digital and the analog hardware inthe instrument Each oftheself tests in theTESTALLsequence can be run individually to help isolate the failure Refer to paragraph 7 7 TEST ALL As the TEST ALL sequence is executed the results of each self test is entered in the test log When the sequence is completed the test log is displayed Refer to figure 7 1 4 for the TEST ALL sequence ...

Page 427: ...FAULT ISOLATION Figure 7 1 4 TEST ALL Sequence YES STOP Enter Results of Tests in Test Log Display Test log NO NO STOP Enter failure in Test log Display Test log Instrument Operational MODEL 3562A 7 63 ...

Page 428: ...are used to isolated failures in the display interface circuits on the A8 Global RAM and A17 Display Interface assemblies refer to 8 11 When one of these keys is pressed the HP 1345A display is disabled TEST PROC Thiskeydisplaysthe menu ofsoftkeys usedtotestprocessing assemblies in the instrument TEST FPP This keydisplays the menu of soft keys uSed to testthe A7 Floating Point Processor The FPP fu...

Page 429: ...ading the data back This test does not disturb devices connected to the HP IB connector The HP IB DIAG keytests all of the HP IB circuits and must not be run with devices attached to the HP IB connector The HP IB CONNEC test is used to troubleshoot the A22 HP IB connector Refer to paragraph 8 6 part D for instructions to use the HP IB Connector test TEST SOURCE This key displays the menu of soft k...

Page 430: ...sing external clocks SYNC2 and 10 MHz and then runs again substituting internal clocksforthe SYNC2 and 10 MHz clocks Refer to 8 8 LO DSA PATT 1 This key is used in the A4 Local Oscillator signature analysis tests Refer to 8 8 LO DSA PATT2 This key is used in the A4 Local Oscillator signature analysis tests Refer to 8 8 TEST I N PUT This keydisplaysthe menu ofsoftkeys used in testing and adjustingt...

Page 431: ...ond conversion pass of the ADCs Refer to 8 19 This key displays the menu for the Test and Fault Logs Refer to paragraph 7 15 for a complete description of the Test Log and the Fault Log The CLEAR TEST key is used to clear the Test Log press twice to clear log The CLEAR FAULT key is used to clear the Fault Log press twice to clear log lOOP ON OFF tests andtofind intermittentfailures Referto paragra...

Page 432: ... measurementusingthefixed sinefromtheanalogsource this measurement is used tosetthe common mode rejection DAC on the A33 A35 Inputassemblies Single channeltriggered measurements usingthe calibrator Pseudo Random Noise Source subblock PRN the inverse of the PRN and the 64 kHz square wave Free run frequencyresponse measurementusingthe periodic chirpfrom the analog source Free run measurement using t...

Page 433: ... calibration accuracyfailure means the magnitude or phase values exceeded the following calibration limits Single Channel Flatness 1 5 dBVpk 3 0 dBVpk 400 Single Channel Phase at 0 1 5 If the calibration accuracy failure occurs the failure is entered in the test log and the calibration curves are used in measurement reading Any assembly in the instrument can cause a calibration failure If calibrat...

Page 434: ...ed adjustment refer to Section Ill b TheA30Analog Source A31 Trigger A32 A34ADCs ortheA33 A35 Inputassemb lies are failing Follow the procedure in paragraph 7 8 Isolating Front End Failures and look for amplitude variations If the assemblies self tests pass but there is a Calibration Source failure check the instrument strigger circuits referto 7 11 and the Pseudo Random Noise Sourcesubblock on th...

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Page 439: ...co House Amorsolo Cor Herrera P D Box 220 15 A M Street T huobah Northrop Instruments Systems Ltd Legaspi Village Makati AL KHOBAR Sturdee House P D Box 1510 Tel 895 1760 895 1764 85 87 Ghuznee Street Metro MANILA Telex 671 106 HPMEEK SJ P O Box 2406 Tel 85 35 8 1 85 34 91 85 32 21 Cable ELECTA AL KHDBAR WELLINGTON Telex 3274 ONLlNE CH CS E M MOROCCO Tel 850 09 1 A CH CS E M Modern Electronic Esta...

Page 440: ...068 Box 19 A S 16393SpANGA THAILAND A CH CS E M MS P Tel 08 750 2000 Unimesa Hewlett PackardLtd Telex 854 17886 ElstreeHouse ElstreeWay 30 Patpong Ave Suriwong BO t WD6 1SG Telefax 08 7527781 BANGKOK 5 REHAMWOOD Hers ACHCMCSEMSP Tel 235 57 27 Tel 01 2075000 Telex 8952716 Hewlett PackardSverigeAB Telex 84439 Simonco T H Frotallisgatan30 Cable UNIMESA Bangkok E CH CS P S 42132VASTRA FROLUNDA A CH CS...

Page 441: ...RG11 3LL Telex 910 325 6608 Hewlett PackardCo Tel 0344 773100 CH CM CS MP Hawaii 1775Minuteman Road Telex 84B805 Hewlett PackardCo ANDOVER MA01810 CH CS E P Hewlett PackardCo KawaiahaoPlaza Suite 190 Tel 617 682 1500 3155PorterOaksDrive 567SouthKingStreet A C CH CS CM E MPr IRELAND PALO ALTO CA94304 HONOLULU HI96813 Hewlett PackardCo NORTHERN IRELAND Tel 415 857 8000 Tel 808 526 1555 32HartwellAve...

Page 442: ...74 1700 CLARENCE NY 14031 Tel 918 665 3300 A CH CS E MS Tel 716 759 8621 A CH CS M Virginia CH Oregon Hewlett PackardCo Hewlett PackardCo Hewlett PackardCo 4305CoxRoad 200CrossKeysOfficePark 9255S W PioneerCourt GLENALLEN VA23060 FAIRPORT NY 14450 P O Box328 P O Box9669 Tel 716 223 9950 WILSONVILLE OR97070 RICHMOND VA23228 CH CM CS E MS Tel 503 682 8000 Tel 804 747 7750 Hewlett PackardCo A CH CS E...

Page 443: ...As changes are made in the instrument to improve per formance and reliability the appropriate pages will be revised to include this information I W ARNING To prevent potential fire or shock hazard do not expose instrument to rain or moisture Manual Part No 03562 9001 0 Microfiche No 03562 9021 0 Copyright 1 985 Hewlett Packard Company 8600 Soper H i l l Road Everett Washington 98205 1 298 USA Pri ...

Page 444: ...r programming instructions due to defects in materials and workmanship If H P receives notice of such defects during their warranty period H P shall repair or replace software media and firmware which do not execute their program ming instructions due to such defects HP does not warrant that the operation of the software firmware or hardware shall be uni nterrupted or error free LIM ITATION OF WA ...

Page 445: ...ammable gases or fumes Operation of any electrical instru ment in such an environment constitutes a definite safety hazard KEEP AWAY FROM LIVE CIRCU ITS Operating personnel m ust not remove instrument covers Component replacement and internal adj ustments must be made by qual ified maintenance personnel Do not replace components with power cable connected Under certain conditions dangerous vo ltag...

Page 446: ... a fau lt A term inal marked with this symbol must be con nected to ground in the man ner descri bed in the i nstallation operat in g manual and before operating the eq ui pm ent Frame or chass is term inal A connection to the frame chassis of the eq uipment which normally incl udes all exposed metal structu res Alternating cu rrent power li ne Direct cu rrent power l i ne Alternating or d i rect ...

Page 447: ... Analog Source A31 Trigger A32 A34 Analog Digital Converter A33 A35 I n put Tables Title Digital Source Functions Digital Sou rce Diagnostics Digital Source Fail ures Effective Sample Rate Generator Test DS Signature Analyzer Setu p DS Signatur e Analysis Test 1 DS Signature Analysis Test 2 DS S ignatu re Analysis Test 3 DS S ignatu re Analysis Test 4 Digital Sou rce Waveforms After Repair Adj ust...

Page 448: ...r Signature Analysis Test 2 D isplay Control ler Signature Analysis Test 3 G lobal RAM Signature Analyzer Setup G lobal RAM Signatu re Analysis Test 1 G lobal RAM Signature Analysis Test 2 G lobal RAM Signal Waveforms After Repair Adjustments and Tests FFT Signature Analyzer Setup 1 FFT Signature Analysis Test 1 FFT S ignature Analyzer Setup 2 FFT Signature Analysis Test 2 FFT Signature An alyzer ...

Page 449: ...rms After Repair Adj ustments and Tests Figures Title Sine Wave Random Noise Burst Random 1 Burst Random 2 Source Trigger Troubleshooti ng Proced u re Diagram D isplay of Verification Pattern H P 1 345A Removal Mother Board Component Locator Troub leshooti ng Procedure Diagram Troubleshooting Procedure Diagram Fault L E Ds Troubleshooting Procedure Diagram Troubleshooting Proced ure Diagram Trigge...

Page 450: ......

Page 451: ... and schematics in Section IX with each of the troubleshooting procedures For the location of cables and boards refer to figure 4 1 in Section IV For the circuit block diagrams refer to Section VI To understand the instrument s operation and signal mnemonics refer to Section VI There are two types of keys on the H P 3562A hard keys and soft keys I n this section the hard keys are in bold text and ...

Page 452: ...is manual I WARNING I Service procedures described in this section are performed with the protective covers removed and power applied Hazardous voltage and energy available at many points can if contacted result in personal injury CAUTION Do not insert or remove any circuit board in the HP 3562A with the Iine power turned on Power transients caused by insertion or removal may damage the circuit bo...

Page 453: ...embly is to use signature analysis and the waveforms provided in parts E and F Start troubleshooting by using part A Digital Source Diagnostics to isolate the failure to a subblock For the component locator and schematic refer to Section IX For the location of cables and boards refer to figu re 4 1 in Section IV Use the oscilloscope waveforms in table A1 10 to see correct operation at various test...

Page 454: ...Digital Source Functions Function Failing Probable Cause or Defective of Failure Triggered Mode Phase Resolution Circuit go to part E Single Channel Phase Phase Resolution Circuit go to part E CNTCLK Control Registers go to part E step 7 Si ne Wave Output La I nput Receiver go to part E Source E nergy Measurement Effective Sample Rate Generator fails 2 41 but random noise go to part D operates at ...

Page 455: ...8 7 U208 5 U208 4 Status Registers Go to part E U1 01 7 Timing Control Circuit Go to part D U206 9 Control Registers Go to part E step 7 U202 1 2 Burst Control Circu it Go to part E step 5 U209 6 Mu ltipl ier Go to part E U1 3 1 3 LO I nput Receiver Go to part E U31 1 11 Noise Generator Go to part E step 8 U1 06 8 Control Registers Go to part E step 7 U5 1 4 Phase Resolution Circu it Go to part E ...

Page 456: ... subblock use table A1 3 after perform ing the following steps 1 Connect the front panel source output to channel 1 2 Connect the rear panel SYNC OUT output to channel 2 3 Press the HP 3562A keys as fol lows PRESET RESET RANGE 5 6 V SOU RCE SOURC E LEVEL 5 V MEAS DISP SCA LE FIXED S I N E 1 kHz FI LTRD I N PUT Y FIXD SCALE T I M E R E C 1 6 6 V Refer to figu re A1 1 to verify resu It NOTE The free...

Page 457: ... f I I I V O O v l p f f f I I I I I I I V V V S e c If the figure A1 1 is correct the fol lowing subblocks are verified LO I nput Receiver Mu ltipl ier Timing State Machine U3 4 Press the HP 3562A keys as follows SOU RCE RANDOM NOISE Refer to figure A1 2 to verify resu lt SERVICE f I V V B O m 8 7 ...

Page 458: ...block is verified Noise Generator O m 5 The random noise shou ld follow the frequency span as it is changed The display shou ld appear similar to figure A1 2 as the frequency span is changed To change frequency spans press the H P 3562A keys as fol lows FREQ FREQ S PAN 1 kHz 1 0 kHz 50 kHz If the random noise follows the frequency span the fol lowing subblock is verified Effective Sample Rate Gene...

Page 459: ... 2 Y FIXD SCALE 6 6 V A B SOU RCE BURST RAN DOM Refer to figu re A1 3 to verify resu It F I L T __ __ __ __ __ r __ __ __ __ __ 6 0 R e a l v 6 0 F x d y L o o L L L L s e L c L L L m F I L T T I ME2 6 0 R e a l v 6 0 O O v l p F x d y L o 0 L L L L S e L c L L L L 8 0 m Figure A1 3 Burst Random 1 SERVICE 8 9 ...

Page 460: ...x d Y 0 0 Figure A1 4 Burst Random 2 2 5 ENTER e c O Ov l p S e c B O m If figures A1 3 and A1 4 are correct the fol lowing subblock is verified Burst Control Circuit 7 Press the H P 3562A keys as follows SOU RCE FIXED SE LECT TRIG S I N E SOURC E TRIG 1 kHz The source trigger point may vary on the sine wave but the trigger point on the SYNC OUT waveform shou ld be the same as displayed in figu re...

Page 461: ...l v 6 0 F x d Y 0 0 F I L T T I M E 2 6 0 1 Re a l v 6 0 Fx d Y 0 0 Figure A 1 5 Source Trigger O Ov l p S e c O O v l p S e c If figure A1 5 i s correct the fol lowing subblock i s verified Phase Resolution Circuit SERVICE B O m B O m 8 1 1 ...

Page 462: ...Test Fails Bits 6 9 1 0 Go to part El Digital Source FIE I nterface Passes LO Input Receiver Digital Source Counters Pass Go to part El Digital Source Main Test Fails Bits 9 1 0 Functions Sine Output is defective but Burst Random and SYNC OUT operate D igital Source FIE I nterface Passes Timing Control Circu it Digital Source Counters Pass or Fail LO Input Receiver Mu ltip lier Digital Source Main...

Page 463: ...m I nterface Bits Multiple Failures Device Decoder PAL or Buffer Programmable Counters Functions Status Registers No functions operate Test Registers Control Registers Latches Go to part Cl C Multiple Failures Test This test verifies the DS data bus the system interface and the device decoder PAL and buffer 1 Press the line switch off Place the A1 Digital Source on the 03562 66540 extender board 2...

Page 464: ... to verify the following signals are the correct TTL level U303 pin 1 2 H igh 1 3 Toggling 1 4 H igh 1 5 H igh 1 6 Toggling 1 7 Toggling 1 8 Toggling 19 Toggling 7 Use a logic to verify the DS data l i nes are togging FR END INTFCE in loop mode Some of the lines will toggle slowly Use the following test locations U406 pins 1 and 11 through 1 9 U405 pins 1 1 through 1 8 8 Press A2 S1 After the powe...

Page 465: ... 0 1 256 kHz 100 kHz 1 1 0 5 1 2 MHz If the fault has not been found go to part E E Digital Source Signature Analysis Tests Use these tests and the waveforms in part F to isolate a fai lure on the digital source assembly Only the components in the failing subblocks need to be tested 1 Press the l ine switch off 2 Connect the Signature Analyzer as fol lows Table A1 5 OS Signature Analyzer Setup Sig...

Page 466: ... 5 P09H U2 11 9765 U8 1 2 9206 1 3 HA1 F 1 4 6P24 1 5 41 CF U9 U3 12 AU9H 1 3 460C 1 4 1 2C3 1 5 49H2 1 6 C26H U1 0 1 7 2 F90 1 8 H166 1 9 2 FP4 U4 3 36UF 6 H1 66 8 OUH3 11 H PC5 U11 US 1 2 H10F 13 5791 1 4 H10F 1 5 9AUF 1 6 6866 1 7 97C4 1 8 H1 66 1 9 3486 U1 2 U6 3 H10F 6 H1 0F 8 21 F2 11 H166 Pin Signature 8 0000 9 H1 66 1 0 5791 1 2 H166 1 3 H10F 5 61 5F 6 C03A 8 006A 9 H10F 5 F4U5 6 1 593 8 C...

Page 467: ...A58 U1 1 2 1 2 H1 66 b 1 3 H1 66 Rev A 1 4 1 5 1 0AH 1 6 1 7 C367 1 8 H1 66 1 9 C367 0000 U11 3 1 2 0000 U201 1 A75U 4 7639 1 0 0000 1 3 H1 66 U202 6 H1 66 1 0 5791 H1 66 U203 2 H10F 6 9 H1 66 1 2 5791 1 6 H10F H10F U204 2 5 H1 66 1 5 H1 66 1 6 1 AUA U209 6 C4A8 6381 U302 4 881 5 8 U H H U 1 0 F73A HA48 54U1 b See backdating SERVICE Signature 561 2 2FU6 UHAP 858P 561 2 2FU6 UHAP 858P 1 27P 8340 77...

Page 468: ... 6 1 4 81 1 H 1 7 1 5 F6P2 1 8 1 6 81 1 H 1 9 1 7 77P7 1 8 304P 5 To start signature analysis test 2 perform the following steps a Press the line switch off b Set A1 J3 to test position c Press the l ine switch on d Press the HP 3562A keys as follows SPCl FCTN SERVIC TEST NOTf LOOP ON TEST SOURCE OS Signature Analysis Test 2 disables the feedback loop between the burst state machine U1 02 and the ...

Page 469: ...A1 S 5 V Signature H1 66 IComponent Pin Signature U1 02 P7SH 1 3 1 9C5 1 4 45C7 1 5 02PU 1 6 SUA9 1 7 PAS8 1 8 H1 66 1 9 H1 66 6 Put jumper A1 J3 in normal N position Component U30S Pin 1 3 1 7 7 To start signature analysis test 3 perform the following steps a Set A1 J 3 in normal N position b Press A2 S1 c Press the H P 3562A keys as follows SPCL FCTN SERVIC TEST LOOP ON TEST SOURCE Signature 7U6...

Page 470: ...207 6 P7CC 8 0000 9 3U2P U208 1 0 7FP2 11 6H62 U1 06 8 C49A U302 U1 09 3 083A U204 1 088C 2 0000 5 8FFP 6 OUA9 9 U039 1 2 CCC3 1 5 0000 1 6 0000 1 9 0000 Pin 11 1 3 7 9 7 9 4 5 6 7 8 8 To start signature analysis test 4 perform the fol lowing steps a Press the l ine switch off b Connect U311 pin 1 0 to TP1 5 c Press the l ine switch on d Press the HP 3562A keys as fol lows SPCl FCTN SE RVIC TEST L...

Page 471: ... 0000 5 5 2HP4 6 6 0000 7 9 7P38 9 1 2 F2CC 1 5 1 5 08P1 1 6 4H58 U41 1 1 1 9 1 AA4 2 3 U21 2 1 7CCO 4 4 6HU7 5 1 0 F4PF 6 1 3 F322 7 9 U31 0 2 C03A 1 5 5 8C04 6 05FC U41 2 1 9 6678 2 1 2 9508 3 15 2777 4 1 6 4CP8 5 1 9 HOFU 6 7 U31 1 2 0000 9 3 A431 1 5 1 1 H1 66 U41 3 1 U31 2 1 23CH 2 4 60FC 3 1 0 37PF 4 1 3 UA63 5 6 U31 3 9 7753 7 1 0 H H05 9 1 1 5C09 1 5 1 3 1 PF9 SERVICE Signature 4F1 3 2F4F ...

Page 472: ... available at man y points can if contacted result in personal injury Table At tO Digital Source Waveforms All jumpers should be in normal position Connect ground to A1 TP1 or A1 TP1 5 Probe 10 1 Press the keys as follows SPCl FCTN sERVIC TEST Important Setup Parameters CNTlD and CNTClK Time Relationship Connect CH1 to A1 TP1 0 Connect CH2 to A1 TP1 1 Oscil loscope LOOP ON TEST SOURCE OVd 1 I Wave...

Page 473: ...hip Connect CH1 to A1 TP2 Connect CH2 to A1 TP3 Duty Cycle Oscilloscope CH1 V Diy 200 mV Div CH2 V Diy 200 mV Div CH1 Coupling dc CH2 Coupl ing dc Time Div 200 ns Div Trigger CH1 NCLK and NSYNC Time Relationship Connect CH2 to A1 J 701 3 Connect CH2 to A1 U1 1 2 Oscil loscope CH1 V Diy 200 mV Div CH2 V Diy 200 mV Div CH1 Coupling dc CH2 Coupl ing de Time Div 2 ms Diy Trigger CH1 Waveform r 1 OVdc ...

Page 474: ...iy 200 mV Div CH2 V Diy 200 mV Div CH1 Coupl ing dc CH2 Coupling dc Time Div 500 JLs Div Trigger CH1 Press the keys as follows FREQ FREQ SPAN 10x Effective Sample Rate Connect CH1 to A1 TP1 2 Oscil loscope CH1 V Diy 1 00 mV Div CH1 Coupl ing dc Time Div 10 JLs Div Trigger CH1 Important Parameters Time Relationship 1 kHz Time Duty cyle After viewing waveform press MAX SPAN oJ I OVdc l I I OVdc MOD ...

Page 475: ...Important Setup Parameters Waveform Connect the front panel source output to external trigger and channel 1 Press the keys as fol lows SOU RCE SOURCE LEVEL SElECT TRIG EXT lrRIG Time Connect CH1 to A1 US 7 Duty Cycle Oscil loscope CH1 V Diy 1 00 mV Diy CH1 Coupl ing dc Time DiY 2 ms Diy Trigger CH1 5 V FIXED S I N E OVdc 7 1 25 Hz SERVICE r 8 25 ...

Page 476: ... TEST ALL Adjustments None I I I Performance Tests 1 1 I f the noise generator su bblock was repaired perform the Source E nergy Measurement test Operational Verification 1 1 I f the phase resol ution circu it was repaired perform the Signal Channel Phase Accuracy test If the LO I nput Receiver was repaired perform the Source Ampl itude Accuracy and Flatness test MODE L 3562A ...

Page 477: ...using figu re A2 1 This procedure diagram describes the best order to perform the troubleshooting tests based on the symptoms observed For the component locator and schematic refer to Section IX For the location of cables and boards refer to figure 4 1 in Section IV Use the oscilloscope waveforms in table A2 5 to see correct operation at various test points in the assembly Use table A2 6 to determ...

Page 478: ...o System CPU Diagnostics B Refer to CPU Global Bus I nterface Test C Refer to H P I B Test D Refer to nonvolatile RAM Test E Figure A2 1 Troubleshooting Procedure Diagram YES MOD E L 3562A Replace all jumpers to normal N position Refer to after repair adjustments and test H ...

Page 479: ...do the fol lowing at power up or when the CPU is reset by pressing A2 S1 1 Flashes the LEOs and then turns each one on starting with 053 1 MSB 2 Clears the test log 3 Stores address and contents of NVRAM 4 Check sums the monitor ROM 5 Exercises several system processor U1 00 instructions 6 Tests the monitor RAM by writing and reading patterns to and from it 7 If an error was found in the RAM test ...

Page 480: ...w byte MEMOL fails Monitor RAM Test Both MEMOL bytes fail Monitor RAM Test H igh byte MEM1 L fails Monitor RAM Test Low byte MEM1 L fails Monitor RAM Test Both MEM1 L bytes fail Monitor RAM Test H igh byte MEM2L fails Monitor RAM Test Low byte MEM2L fails Monitor RAM Test Both MEM2L bytes fail Monitor RAM Test Multiple Monitor RAM failures Monitor RAM Test NVRAM high byte fails Monitor RAM Test NV...

Page 481: ...h on Hex Code Explanation Unexpected timer interrupt Timer interrupt fai lure Timer Failure H P I S Failure 4 Put A2J8 A2J1 2 A2J1 3 and A2J1 7 in test T position Most likely Failure A2 U500 U41 3 A2 U500 U41 3 A2 U1 00 A2 U41 3 H P I S subblock 5 Repeatedly press the reset switch S1 while checking for TTL levels of the global bus drivers latches and control subblocks D HP IB Test 1 To test the H ...

Page 482: ... remove the A22 HP B board E Nonvolatile RAM Test 1 Check the following for correct value location U211 28 U21 2 28 U211 26 U21 2 26 Value 4 5V 4 5V TTl logic 1 TTl logic 1 2 Press the l ine switch off With the power off U211 28 shou ld be greater than 3V 3 Connect the signature analyzer according to table A2 2 4 Check the signatu res of A2 U408 6 and A2 U305 1 5 they shou ld be the same F CPU Sig...

Page 483: ... Jumpers i n either normal o r test position A2J1 5 A2J16 Signature Analyzer Setup Refer to table A2 2 5 V Signature 0001 Component Pin Signature Component U1 00 29 UUUU U100 30 5555 31 CCCC 32 7F7F 33 5 H21 34 OAFA 35 UPFH 36 52F8 Pin Signature 37 HC89 38 2H70 39 H PPO 40 1 293 41 HAP7 42 3C96 43 3827 44 755U Put jumper J1 in position 1 It takes about 1 0s for each of the following signatures to ...

Page 484: ...OM Test Jumpers in test T position A2J4 A2J5 A2J 6 A2j 7 A2J9 A2J10 A2J18 Jumpers in position 2 A2J1 A2J11 A2J14 J umpers in normal N position A2J 8 A2J1 7 A2J1 2 A2J 1 3 J umpers in either normal or test position A2J1 5 A2J1 6 Signature Analyzer Setup Refer to table A2 2 5 V Signature 6PCP Component Pin Signature Component U1 05 1 1 9UUU U205 1 2 FH2H 1 3 H H H H 1 5 P488 1 6 F7CH 1 7 H1 HA 1 8 C...

Page 485: ...1 to A2 TP5 Oscil loscope f I f I Bandwidth Limit ON J J J Mode A CH1 V Diy 50 mV Div lr J CH1 Coupling dc OVdc W W M T C H I Time Div 50 ns Div M a l n 5 121 n s 0 1 V Trigger CH1 1 Press A2 S1 switch to see the waveform 2 DTACKL and ASL will stop changing for a short time 2s DTACKl ASl Time C H I C P L G D C C H 2 C P L G D C relationship C H 1 1 0 0 m V D l v C H 2 1 121 121 m V O i v Connect C...

Page 486: ...relationship C H 1 2 121 121 m V D l v C H 2 2 121 121 m V D l v Connect CH1 to A2 U1 00 1 9 Connect CH2 to A2 U1 00 20 I OVdc I Oscilloscope Mode A B r r r CH1 V Diy 200 mY Diy CH2 V Diy 200 mY DiY OVdc CH1 Coupl ing dc CH2 Coupling dc M T C H I Time Div 1 0 j ts Div M a n I u s D i y Trigger CH1 3 Press RETURN LOOP OFF ERROUT Time C H I C P L G D C C H I 1 121 121 m V D t v Connect A2 TP6 to A2 ...

Page 487: ... H J fter Repair Adjustments and Tests Table A2 6 After Repair Ad justments and Tests Perform the following Section Diagnostic Tests TEST ALL V I I Adjustments None Performance Tests None MODEL 3562A 8 37 8 38 ...

Page 488: ......

Page 489: ...Diagnostics Refer to Section IX for the component locators and schematics refer to figu re 4 1 in Section IV for location of cables and boards Use table A3 3 to determine which adjustments and tests need to be performed to complete instrument service Troubleshooting Hint The ROM board is very sensitive to changes in 5 V Check this voltage before proceeding with the rest of this section A IProgram ...

Page 490: ...ROM Bus failure high byte 2 7C ROM Bus failure both bytes 3 SA Check ROM failure low byte 3 5 B Check ROM fa ilure high byte 3 5C Check ROM failure both bytes 4 40 to 53 ROM IC failure low byte 4 20 to 33 ROM IC failure high byte 4 60 to 73 ROM IC failure both bytes 4 84 ROM ICs mu ltiple failures high byte 4 85 ROM ICs multiple failures low byte 4 86 ROM ICs multiple failures both bytes 4 8D No R...

Page 491: ...U11 1 A U11 2 B U1 1 3 C U114 D U1 1 S E U11 6 F U11 7 3 0 U11 8 1 U11 9 2 U120 3 B I fter Repair Adjustments and Tests Table A3 3 After Repair Adjustments and Tests Perform the following Section Diagnostic Tests Test All V I I Adjustments None Performance Tests None SERVICE Suspect IC U201 U202 U203 U204 U20S U206 U207 U208 U209 U21 0 U21 1 U21 2 U21 3 U21 4 U21 S U21 6 U21 7 U21 8 U21 9 U220 8 4...

Page 492: ......

Page 493: ...oards How to Use This Section Star t Reh rence Verify Aft r Repair The primary troubleshooting method for the LO assembly is to use the self tests to determine which subblocks and possible components are failing Signature analysis is then used to troubleshoot the individual subblocks suspected of failing Start troubleshooting by using part A Local Oscillator Diagnostics For the component locator a...

Page 494: ... failure is A4 U36 and U37 in the system bus interface or A4 U55 U56 U68 U46 U51 and U1 4 in the control and timing circuits 2 I nternal and External Clocks The external clock test uses the 1 0 24 MHz clock from the A31 Trigger and the SYI lC2 from the A6 Digital Filter normal operating clocks The internal clock test substitutes these clocks for clocks generated on the LO assembly The internal clo...

Page 495: ...s to the components are correct the failure is most l ikely caused by the phase accumu lator LO DSA PATT 2 The phase accumulator feeds its output back to the input LO DSA PATT 2 breaks this feed back loop Start by checking the signatures of A4 U11 and U1 6 Check the signatures of the other components i n the phase accumulator by moving forward and back from A4 U11 and U1 6 4 Output Value Fai lures...

Page 496: ...ing between TTL level high and TTL level low 1 Press the l ine switch off 2 Connect the Signature Analyzer as fol lows Table A4 1 A4 Signature Analyzer Setup Signal Polarity Ground Clock Positive edge Stop Negative edge Start Positive edge 3 Press the line switch on 4 Signature Analysis Test 1 Setup a Press the keys as follows SPCl FCTN SERVICE TEST Connection A4 J1 1 A4 J1 3 A4 1 4 A4 1 5 LOOP ON...

Page 497: ...C 1 2 882A 1 3 3P1 H 1 4 A1 3 P 1 7 756P U24 U1 9 2 OF06 3 392U 4 06UC 5 3CP5 6 34H8 7 9631 8 45FP 9 C4A9 1 2 6022 U25 1 3 1 4U8 1 4 698A 1 5 AC37 1 7 F792 1 8 U534 1 9 AC37 A See backdating SERVICE Pin Signature 1 1 P1 A2 1 2 9149 1 3 P43P 1 5 9C68 1 6 1 2CO 1 7 2H8P 1 8 6C7P 1 9 6PA1 1 2 4373 1 3 U981 14 7F65 1 5 0097 1 6 OPF4 1 7 ASAP 1 8 P320 1 9 81 97 1 2 91 48 1 3 6303 1 4 46FU 1 5 3CC9 1 6 ...

Page 498: ...3 1 1 C0 4 1 5 6582 5 1 6 P104 8 1 7 4791 9 1 8 09AF 1 1 1 2 3 8HC6 1 3 6 8U6F 14 1 0 4UOC 1 5 1 5 1 622 1 6 1 7 1 1 U21 P 1 8 1 2 0000 T 1 9 1 3 0000 T 1 4 P43F T U41 1 45FP 1 5 P43F T 2 1 6 P43F T 3 1 7 0000 T 4 1 8 0000 T 5 6 1 1 P43F T 7 1 2 P43F T 1 1 1 3 0000 T 1 2 1 4 0000 T 1 3 1 5 P43F T 1 4 1 6 P43F T 1 5 1 7 0000 T MODE L 3562A Signature 3UAH 1 9H7 A61 6 1 903 H1 F3 5263 9AA3 1 1 1 U P4...

Page 499: ... 6 21 57 13 1 7 OA73 1 4 1 8 84AO 1 5 1 9 7U65 1 6 1 7 1 2 OA5H 1 8 1 3 A39C 1 9 1 4 52PH 1 5 C7AP U58 2 1 6 O H U U 3 1 7 OAA9 4 1 8 F6UH 5 1 9 7874 6 7 1 2 553C 8 1 3 569U 9 1 4 2FF3 1 2 1 5 22A3 1 3 1 6 7FPF 1 4 1 7 AAAC 1 5 1 8 OU04 1 6 1 9 U P9H 17 18 5 A451 1 9 6 U FAC U62 5 2 OP31 6 5 A1 C7 6 732U SERVICE Signature 8956 2278 9398 96A7 06A8 OF8F 2AU6 1 4UC 4COA 373H 7261 C1 PO 8944 96A7 9398...

Page 500: ...1 2 FU1 H 1 3 2UF6 1 4 1 01 U 1 5 648H 1 6 P732 1 7 4UAF 1 8 4331 1 9 HH5P 6 Signature Analysis Test 2 Setup a Press the keys as fol lows SPCl FCIN SERVICE TEST Component U71 U72 U75 LOOP ON TEST SOURCE Pin 2 3 5 9 1 1 1 2 1 2 5 5 7 9 MOD E L 3562A Signature 64CO P43F CP34 OHC3 P43F T UFAC A7A3 P43F 4PUP A1 C7 OP31 C6AH LO DSA PATT 2 ...

Page 501: ...1 1 7F34 U1 6 U4 4 APU2 7 52C8 9 94AP 1 2 P27U US 2 CH7A U1 9 5 CH7A 6 CH7A 9 CH7A 1 2 CH7A 1 5 CH7A 1 6 CH7A 1 9 CH7A U57 U6 2 OUHU 5 356P 6 9P67 9 3845 1 2 F6F8 U65 1 5 6HF1 1 6 60PA 1 9 3845 U7 5 U824 7 5966 9 8051 11 APAC SERVICE Pin Signature 5 4F8H 7 28F8 9 035U 1 1 APAC 4 6494 7 P380 9 83UC 1 2 P27U 5 1 PCC 7 1 A75 9 U699 1 1 1 4H2 1 A143 4 C2P2 9 1 61 P 1 0 897A 1 3 OU63 1 A037 4 2A68 9 06...

Page 502: ... many points can if contacted result in personal injury Probe 10 1 Setup SYNC2 and COS Connect CH1 to A4 TP8 Connect CH2 to A4 TP24 Oscilloscope Table A4 4 LO Signal Waveforms Important Parameters Time relationship Waveform Pulse shapes OVd 1 1 1 W I I CH1 V Diy CH2 V Diy CH1 Coupling CH2 Coupling 200 mV Diy 200 mV Diy dc dc OVd II I I Time Diy 1 p s Diy Trigger CH1 1 SYNC2 and N LD Time relations...

Page 503: ...ou pling dc CH2 Cou pling dc Time Div 500 ns Div Trigger CH1 3 SYNC2 and LDOUT Time relationship Connect CH1 to A4 TP8 OVde I I I I I I I I1 I 1 Connect CH2 to A4 TP11 Osci I loscope CH1 V Diy 200 mV Div OVde I I H I H I CH2 V Diy 200 mV Div CH1 Coupling dc CH2 Coupling dc Time Div 1 fl s Div Trigger CH1 4 E Time Connect CH1 to A4 TP2 fv JiV Oscilloscope CH1 V Diy 1 00 mV Div OVdc A A j _I CH1 Cou...

Page 504: ... 200 mV Div CH2 V Diy 200 mV Div Vdc n I CH1 Coupl ing dc CH2 Cou pling dc Time Div 1 p s Div Trigger CH1 Waveform I In I 6 D After Repair Adjustments and Tests 8 54 Table A4 S After Repair Ad justments and Tests Perform the following Section Diagnostic Tests V I I L O FU NCTN TEST ALL Adjustments I I 1 N one Performance Tests 1 1 None Operational Verification 1 1 None MODE L 3562A I I t ...

Page 505: ...e Reference Afh r Repair Begin with troubleshooting hint 1 If the failure is determined to be on the DFA perform the DFA diagnostic self tests while keeping track of the subblocks that are verified and the signals that are failing Check the clocks and signals l isted in the Signal Verification paragraph After determ ining the possible defective subblocks use signature analysis to isolate the fai l...

Page 506: ...kes used to access this diagnostic are PRESET RESET SPCl FCTN SERVIC TEST TEST I N PUT A DFA Diagnostics ADC D IGTAL TEST The diagnostic tests for the Digital Filter Assembly al low you to test groups of circu its to further isolate a problem A subset of the DFA diagnostic tests run when the nstrument power is tu rned ON during SELF TEST and during TEST ALL Display the DFA diagnostic test menu usi...

Page 507: ...errupt tests refer to the types of interrupts used to perform the measurement Data is transferred from global RAM into the digital filter control ler where it may or may not be fi ltered depending on the type of measurement required There is an interrupt indicating end of measurement for each of the the two cases If either of the interrupt tests fail test the local bus first and then the DMA bus w...

Page 508: ... DFA functional diagnostic test except that it uses a constant signal instead of the LO signal for the zoom process This means that the fundamental signal is outside the zoom window subharmonics are all that are measured but the measurement resu lts are pred ictable to the point that individual bits may be checked The results of the filtering are stored in global RAM The system CPU then performs a...

Page 509: ...est If the test still fails start troubleshooting the system data bus interface and data point counter block on the A6 board If the test passes with the AS board removed the fai l u re is on the AS assembly replace the AS assembly and continue with the diagnostic tests If Cl bit passes any of the echos tests the bus line transm itting that bit is good If that bit is bad on every test the bus l ine...

Page 510: ...ntrol IC correspond ing to the channel that failed the measurement fai led to set up Writing wrong data causes the message DFA Filter Bus x to be displayed and ind icates a problem with the interface IC associated with the fai ling channel If the filter bus test passes the fol lowing circu its and processes are probably fu nctioning correctly Paral lel I nput Control G lobal Bus DMA Control Global...

Page 511: ...seband real data only Failure messages tell you three things which of the five tests fail these are cal led DFA Transient Tests which channel and fi lter IC fail e g CH1 Real Filt and which bits fail The filter ICs are duplicate parts mounted in sockets al lowing you to switch parts between channels to verify fai lures When the test is run with loop mode on the first transient test only is perform...

Page 512: ...e then the channel 1 and channel 2 digital filters are accepting data If the digital filters are not accepting data the pu lses occur at a 51 2 kHz rate 4 Verify the SYNC2 signal at AS U401 20 and AS U41 5 20 waveform 4 table A5 1 The SYNC2 signals are only active when the digital filter has accepted a data point 5 Verify the fol lowing bus requests from the filter controls see waveform 5 table A5...

Page 513: ...t Ch 1 to AS TP1 Connect Ch 2 to AS TP2 Table AS l Oscilloscope Signal Waveforms Important Parameters Waveform Time I t Phase Cj Channel 2 Levels I C C Cl l Scale 4 V div Timebase 1 00 ns div Offset O V Coupling dc 1 CH1 j 1 CH2 j 1 Connect Ch 1 to AS TP1 Time f C F LC fj Connect Ch 2 to AS TP3 Phase Scale 4 V div f tC rj Timebase 1 00 ns div Levels Offset O V Coupling dc 2 CH1 SH IFT1 CH2SH IFT1 ...

Page 514: ... Scale 2 V div Timebase 1 p s div Offset O V Coupl ing dc 4 CH1 BR2 CH2BR2 CH1 BR3 CH2BR3 Channel 1 Time Connect Ch 1 to AS U401 34 or 47 Channel 2 Connect Ch 1 to AS U41 S 34 or 47 Scale 2 V div Timebase 1 00 ns div Offset D V Coupl ing dc 5 CH1 10EN Connect Ch1 to AS TP1 8 Time I Scale 2 V div Timebase 1 p s div Offset O V Coupl ing dc 6 r r ...

Page 515: ... the test you wish to perform Move jumpers as instructed at the beginning of the test Connect the power cable and turn on power I nitiate the DFA PATT test as instructed at the beginning of the test To put a test in the loop mode press the SPCL FCTN key select SERVIC TEST and press the LOOP menu key to l ight up ON 1 Signature Analysis Test AS 1 System Interface Control a Put A5J 5 and ASH in test...

Page 516: ... 1 6 1 5 87AP 1 7 1 6 8325 1 8 1 7 87AP 1 9 1 8 83A4 20 1 9 1 6FO 21 22 U41 1 2 9 FAU 3 08A9 4 06U2 5 C970 6 44UC 7 65C1 8 FOA9 9 4C59 11 A826 1 2 A826 1 3 PH9H 1 4 PH9H 1 5 A826 1 6 AA63 1 7 A826 1 8 AA23 1 9 FF7H e Turn off power Retu rn all jumpers to normal N position 2 Signature Analysis Test AS 2 Channel 1 Digital Filters a Put 17 in Test Position b Connect the signatu re analyzer as fol low...

Page 517: ... 54CA 24 3C53 25 91 1 P 26 7207 27 CP64 28 76H1 29 0738 30 1 7C5 31 34P4 32 F1 5P 45 2595 53 AOU7 54 7P05 55 30P1 56 C6PF 57 25AU 59 2595 60 2595 61 2595 62 2595 Connection TP8 A5 TP1 3 DSASS A5 TP1 3 DSASS A5 U404 1 e Return all jumpers to the normal N position 3 Signature Analysis Test AS 3 Channel 2 Digital Filter a Put J7 in Test Position b Connect the signature analyzer as follows SERVICE 8 6...

Page 518: ...05 55 30P1 56 C6PF 57 25AU 59 2595 60 2595 61 2595 62 2595 e Return all jumpers to normal N position 4 Signatu re Analysis Test AS 4 Channel 1 Global Data Bus I nterface a Put J7 in test position b Connect the signatu re analyzer as fol lows Signal Polarity CND START STOP CLOCK c Put DFA PATT 1 in Loop Mode d Check the signatures in table AS S Connection TP8 A5 TP1 3 A5 TP1 3 A5 TP21 MOD E L 3S62A...

Page 519: ... b Connect the signature analyzer as follows Signal Polarity CND START STOP CLOCK c Put DFA PATT 1 in Loop Mode d Check the signatu res in table AS 6 Connection TP8 AS TP1 3 AS TP1 3 AS TP22 Table A5 6 DFA Signature Analysis Test 5 Component Pin Signature Component 5 V 6PCP U41 3 U31 3 1 4 AUPO 1 5 5A5A 1 6 790C 1 7 6986 1 8 1 86U 1 9 HOHA 20 1 FC9 e Return all jumpers to normal N position Pin 1 3...

Page 520: ...tal Filter Control a Put J2 in Test T position b Connect the signatu re analyzer as follows Signal Polarity CND START STO P CLOCK c Put DFA PATT 2 in Loop Mode d Check the signatures in table AS 7 Connection A6 TP3 A6 TP7 A6 TP7 A6 TP5 MOD E L 3S62A ...

Page 521: ...OH95 31 79 U202 9 49A3 1 3 56H7 U203 5 56A4 AFFF U305 5 AFFF FH76 U207 6 447C 1 0 AFFF 1 5 AFFF AFFF U206 3 AFFF 6 8 56A4 8HU8 U307 6 456C 9 76H2 1 6 07H P H75A U306 2 37F7 3 1 C90 4 U974 5 6 7203 7 4946 8 OAP1 1 2 Toggle 1 3 Toggle 14 Toggle 1 5 648A 1 6 Toggle 1 7 H24P 1 8 897U 1 9 OAP1 OAP1 C22H 6AU7 255C SERVICE Signature OH95 Toggle Toggle H24P Toggle Toggle Toggle Toggle OH95 H24P OH95 OH95 ...

Page 522: ...C HCH 19 21 6U U308 1 2 447C 1 3 FH76 14 1 C90 1 5 37F7 1 6 H75A 1 7 07H P 1 8 76H2 1 9 8HU8 e Return all jumpers to normal N position Pin 9 14 9 1 3 6 8 1 1 E After Repair Adjustments and Tests 8 72 Table AS 8 After Repair Ad justments and Tests Perform the following Section Diagnostic Tests Test All VI I Adjustments None Performance Tests None MOD E L 3562A Signature F474 49A3 3048 49A3 49A3 49A...

Page 523: ...troubleshooti ng by perform ing part A I n itial Conditions Test The primary troubleshooting method for the FPP is to use the self tests to determine which subblocks are operating correctly Signatu re analysis is then used to troubleshoot individual subblocks suspected of fail ing For the compo nent locator and schematic refer to Section IX For the location of cables and boards refer to figure 4 1...

Page 524: ...is not the correct value go to paragraph 8 1 6 A1 8 Power Supply Assembly 5 If the cause of the fai lure is stil l not found go to part B B FPP Diagnostics The FPP is tested using several self tests When a test is initiated the A2 System CPU loads test data and FPP instructions into the A8 Global RAM except in the Reset FPP test and commands the FPP to perform the test After completing the test th...

Page 525: ... displayed press A2 51 to reset the FPP and continue with the self tests 2 If the command pointer test COMAND PO INTR does not complete press A2 51 When the power up tests are completed set jumper A7 j 2 B to test position Press the H P 3562A keys as fol lows SPC l FCTN SERVIC TEST TEST PROC TEST FPP J UMPER ECHO J UMPER ECHO The FPP status LEDs shou ld display 0000 0001 0 off 1 on 3 Use table A7 ...

Page 526: ...to the CPU after runn ing a test Continue with self tests Jumper Echo Test FPP J umper Echo Bits Command Pointer Registers SA 1 correspond to B bus 0 to 1 5 DTACK Ci rcuit SA 2 and Y bus 0 to 23 FPP I nterrupt Circuit SA 3 G lobal Data Bus Output Registers SA 4 Partial verification of ALUs Block Set Test FPP Address Test Bits G lobal Address Registers SA 1 correspond to B bus 0 to 1 5 G lobal Data...

Page 527: ...em CPU The system CPU tests the FPP status in global RAM and any errors in the status are displayed If the interrupt is not received by the system CPU before a countdown loop is completed the system CPU tests the FPP status in global RAM Any errors in the status and an FPP interrupt fai lure are displayed 3 J u m per Echo Test The jumper echo test is used when the command pointer test does not ter...

Page 528: ...hese tests to isolate a failure on the FPP assembly Only the com ponents in failing subblocks need to be tested The term toggling refers to a signal continually changing between TTL level high and TTL level low 1 Press the line switch off 2 Put all jumpers in normal N position 3 Connect the Signatu re Analyzer as follows Table A7 2 A7 Signature Analyzer Setup 1 Signal Ground Clock Stop Start 4 Pre...

Page 529: ...6 951 5 1 7 Toggling 1 8 Toggling 1 9 Toggling U401 1 2 55FA 1 3 OA56 1 4 951 7 1 5 55FC 1 6 Toggling 1 7 951 5 1 8 Toggling 19 Toggling U505 1 FA8A 1 2 1 471 1 3 97H F 1 4 F54F 1 5 9P32 1 6 835C 1 7 C988 1 8 FF2P 1 9 72AA U506 1 2 U1 U9 1 3 5FFF 6 Put all jumpers in normal N position Component U506 cont U507 U41 2 U41 4 U51 0 U51 2 U51 4 Pin 1 4 1 5 1 6 1 7 1 8 1 9 1 9 1 2 3 4 5 6 7 8 9 1 1 2 3 4...

Page 530: ...in U21 2 1 0001 U303 30 2 AC6P cont 31 3 F273 32 4 85AU 33 5 U484 34 6 AC6P 35 7 3 HAH 37 8 C807 38 9 A84C 40 1 1 UFFP 41 1 2 97F3 42 1 3 O U3P 44 1 4 A457 45 1 5 5C87 46 1 6 UOP8 47 1 7 5C86 48 1 8 0000 1 9 0000 U304 3 4 U303 1 97F3 5 2 85AC 6 3 61 8U 1 0 4 OP75 1 2 5 61 8C 1 4 6 OP75 1 6 7 3HAH 1 7 8 6CPA 1 8 9 7CA6 1 9 1 2 2020 21 1 4 HAC5 22 1 5 85AC 23 1 6 1 7F8 24 1 7 46C9 25 1 8 1 7FA 26 1 ...

Page 531: ... 8 Put all jumpers in normal N position 9 Signature Analysis Test 3 Setup Component U308 U31 0 a Put jumper A7 J2A in test position with the power on Pin 1 0 1 2 1 4 1 6 1 7 1 8 1 9 21 22 23 24 25 26 39 40 48 1 0 1 1 1 2 1 4 1 6 1 7 1 8 1 9 21 22 23 24 25 26 48 Signature 81 33 2020 61 97 61 89 U782 61 89 U782 OU38 UFFP 5AAA 99A5 5AAA 99A5 POA5 5C86 U421 3A1 1 Toggl ing 0000 U484 61 89 U782 61 89 5...

Page 532: ...5AH 1 2 F636 1 3 PFHO 14 PFHO 10 Put all jumpers in normal N position 1 1 Signature Analysis Test 4 Setup a Press the line switch off Component U502 b Connect the Signature Analyzer as follows Table A7 6 A7 Signature Analyzer Setup 2 Signal Polarity Connection Ground A7 J 5 1 Clock Positive edge A7 J 5 3 Stop Positive edge A7 TP4 Start Negative edge A7 TP4 Pin Signature 5 7A3F c Set jumpers A7 J3A...

Page 533: ...H62U 35 C21 A 37 HA07 39 HOAA U1 04 9 51 H2 1 0 56U8 11 41 P8 1 3 HAP2 U1 12 1 4 U84A 1 5 4H76 16 A29C 1 7 PU42 U1 05 9 70HA 10 9561 11 99HO 1 3 94A9 U11 3 1 4 C057 1 5 F034 1 6 AAC3 1 7 CU98 U1 06 9 06C1 1 0 1 3U P U114 11 3AHA 1 3 UP7C 14 5C76 1 5 CC55 1 6 4U7A 1 7 36AP SERVICE Pin Signature 9 H52P 10 P67U 11 2443 1 3 UP53 1 4 51 F9 1 5 AC1 A 16 PH5P 1 7 H4U H 9 28F6 10 350P 11 OA71 1 3 P674 1 4...

Page 534: ...taken with a 10 1 probe Other notes unique to a measurement are written next to the waveform I W ARNING Service procedures described in this section are performed with the protective covers removed and power applied Energy available at many points can if contacted result in personal injury T able A7 8 FPP W aveforms Set all jumpers in normal N position Connect ground to A7 TP6 A7 TP11 Probe type 1...

Page 535: ...ents and Tests T able A7 9 After Repair Adjustments and T ests Perform the following Section Diagnostic Tests FPP FUNCTN V I I TEST ALL Adjustments None I I I Performance Tests None I I Operational Verification None 1 1 SERVICE 8 85 8 86 ...

Page 536: ......

Page 537: ...elerence After Repair Start troubleshooting with part A Global RAM Diagnostics Use of this section will isolate the problem to a subblock of A8 or A1 7 Refer to Section IX for the component locators and schematics Refer to figure 4 1 in Section IV for location of cables and boards Refer to figure 7 4 in Section VI I for power up test codes Use table A8 1 0 to determine which adjustments and tests ...

Page 538: ...nreadable Whenever a softkey is used in this section the softkey number 51 through 58 from top to bottom appears in parenthe ses after the softkey name If the G LOBAL RAM test fails read the test log on the 1 345A display and or the hex code from the A2 LEDs Use table A8 1 to find the most likely failure or suggested tests to further isolate the problem Problems in the A8 Display Control section o...

Page 539: ...r ough GD1 S Nonrepeatable Dynam ic RAM chip memory failure associated with fail ing bit bit N GDO through GD1 S address circu it global bus transceivers Global RAM Memory Refresh Timer refresh failure Arbiter Refresh Address Counter G lobal RAM all Memory control circuit bits failed A8 U307 U308 both bytes G lobal RAM all A8 U61 0 U307 U308 bits fai led high byte Global RAM all A8 U609 U307 U308 ...

Page 540: ...tests operation of the arbiter refresh address counter and memory address sections of A8 1 Display Control a Display Refresh Timer Turn on power Using an oscilloscope check the fol lowing clock signals in the Display Refresh Timer circuits block Signal ClK TP3 SYNC b Display Control ler Frequency 8 MHz 61 Hz 61 Hz Check TP5 TP6 and TP7 for the waveforms shown in table A8 9 1 c Display DMA Address ...

Page 541: ...able AB 3 Table AB 3 Display Controller Signature Analysis Test 1 Signal Name le Pin Signature 5 TP2 0001 GA1 L U604 9 UUUP GA2L 8 5554 GA3L 7 CCCA GA4L 6 7F7H GA5L 5 5 H20 GA6L 4 OAFC GAll 3 U PFF GA8L 2 52F9 GA9L U605 9 HC88 GA1 0L 8 2H71 GA1 1 L 7 H PP1 GA1 2 L 6 1 292 GA1 3L 5 HAP6 GA14L 4 3C97 GA1 5L 3 3826 GA1 6L 2 755P If these signatu res are correct proceed to step e Display DMA Word Coun...

Page 542: ... problem is a board trace or solder joint If the signature is also incorrect at the word cou nter proceed with step d Display DMA Add ress Counters d Display DMA Address Cou nters Perform this test only if a failure was found in performing the signature analysis in table A8 4 This test verifies that the address counters are load ing correctly If load ing fai ls either a data receiver cou nter or b...

Page 543: ... LEDs shou ld display hex BB TE5T MEMORY 52 Move jumpers ABj3 and ABj4 to the test T position D5 PINT TEST 1 53 Press softkey 55 A2 LEDs display BA This loads a hex 5 into each of the Display Address Counters U600 through U603 toggling each bit from the previously loaded hex A Probe the output pins of U600 through U603 The output of each cou nter should be hex 5 binary 01 01 pins 1 1 1 2 1 3 and 1...

Page 544: ...lay I nterface board 2 Display I nterface Because of the relative cost of the A17 board and troubleshooting time it is recommended that this board be replaced if defective 3 Global RAM a Setup for G lobal RAM tests Turn off power Move A8J 5 J6 J7 J8 and J9 to test T position J umper J 5 disconnects the memory request lines from the arbiter and routes the output from the refresh address counter int...

Page 545: ...ming Waveform BUS EN 2 table A8 9 6 1 06 MHz square wave 1 06 MHz square wave 1 1 8 kHz positive pulses 1 1 8 kHz negative pulses Set up equ ipment as described in part 3 a above Using an oscilloscope check the fol lowing signals in the global timing circuit block B2GDSL table A8 9 5 GDSL table A8 9 5 GSMP table A8 9 6 If any of these signals are incorrect check the inputs pin 1 and tapped outputs...

Page 546: ...vers CO U1 11 1 3 96PF C1 2 725C C2 5 P5PH C3 9 5CPO C4 U21 1 9 7P25 CS 1 2 85PA C6 5 77F7 C7 2 6PCP MAO U1 11 1 1 2HH8 MA1 3 F96U MA2 6 5PH9 MA3 8 POH4 MA4 U21 1 8 F51 1 MA5 1 1 3PHP MA6 6 FFU3 MA7 3 H58A Memory Address l ines MAO U1 1 0 5 2HH8 MA1 7 F96U MA2 6 5PH9 MA3 1 2 POH4 MA4 1 1 F51 1 MA5 10 3PH P MA6 1 3 FFU3 MA7 9 H58A These eight signatures shou ld be the same for corresponding pins on...

Page 547: ...res in table A8 8 Table A8 8 Global RAM Signature Analysis Test 2 Signal Name le Pin Signature IDLE U509 2 6493 MG B2D2L 3 7820 MGFPP 4 CPA9 MG68L 5 31 H6 MGDF1 6 9502 MG DF2L 7 OCC1 MG FFT 8 96PF MGRFS H L 9 20A7 MG RFSH 1 1 20A7 MG FFTL 1 2 96PF MGDF2 1 3 OCC1 MGDF1 L 14 9502 IMG68L 1 5 31 H6 MGFPPL 16 C PA9 MG B2D2 1 7 7820 I DLEL 1 8 6493 Priority Decoder outputs YA U506 1 9 2 H H8 YB 18 2P36 ...

Page 548: ... Time Pol arity Connect Ch1 to AB TP7 Wd I I I I I I I I I Connect Ch2 to AB TP5 or TP6 Scale 2 V div OVd I1 I 1 IIII I I I i I Timebase 2 JLs div Offset 2 V Trigger Ch 1 Coupl ing dc 1 This series of pu lses repeats every 1 6 4 ms 8202 OSA STOP START Power on Press the fol lowing HP 3562A key sequence SPCL FCTN 5ERVIC TEST 52 TEST MEMORY 52 D5P I NT TEST 1 53 Move ju mpers AB J3 and J4 to test T ...

Page 549: ...ale 1 V div Timebase 200 ns div Offset 2 V Trigger Ch 1 Coupling dc GRAM OSA STOP START Time Connect Ch 1 to AB j2 4 Scale 1 V div Timebase 50 p s div Offset 2 5 V Trigger Ch 1 Coupling dc 1l 2G OSl GOSl Time Connect Ch 1 to U301 B Connect Ch 2 to U306 B Scale 2 V div Timebase 5 p s div Offset 2 V Trigger Ch 1 Coupling dc SVdc OVdc SVdc OVdc OVd 1 Waveform 1fhMr U I Y OW liV 3 11 M i WY IW 0__ _ 4...

Page 550: ...Ch 1 Coupl ing dc 6 MRAS MCAS Time Connect Ch 1 to U307 2 Time Connect Ch 2 to U30B 4 relationship OVd llri I 1 4 t l I Scale 2 V div Timebase 1 00 ns div OVd t f l jr I o Offset 2 V fQt t V Trigger Ch 1 Coupl ing dc 7 CD RAMGR GWL Time Lower byte Time Connect Ch 1 to U609 9 relationship Connect Ch 2 to U609 1 1 OVd Upper byte Connect Ch 1 to U61 0 9 OVd Connect Ch 2 to U610 1 1 Scale 2 V div Time...

Page 551: ...11 Connect Ch 2 to U1 03 1 5 SERVICE I Ii j Upper byte RASUL CASUL OVd V O t t1 Connect Ch 1 to U203 4 Connect Ch 2 to U203 1 5 9 Scale 2 V div Timebase 1 00 ns div Offset 2 V Trigger Ch 1 Coupling dc D After Repair Adjustments and Tests Table AS 1 0 After Repair Adjustments and Tests Perform the following Section Diagnostic Tests Test All VII Adjustments None Performance Tests None 9 8 1 01 8 1 0...

Page 552: ......

Page 553: ... cord from the rear panel and remove the top cover 2 Remove the internal shield covering the display unit 3 Remove the trim strips from the front frame 4 Remove the front frame and side panel screws as shown in figure D 2 5 Remove the screws that attach the display to the instrument as shown in figure D 2 6 Remove the two screws attaching the display adjustments to the rear panel of the instrument...

Page 554: ...SERVICE 8 104 STEP 4 STEP 5 Figure 0 2 HP 3562A Removal STEP 4 TO P VI EW COVER REMOVED x o co w o f Z o Cl w MODE L 3562A ...

Page 555: ...leshoot the FFT board use the FFT diagnostic tests to further isolate the prob lem Circuit descriptions in Section VI provide the background for understanding how the FFT board circu its work Once the problem has been local ized to a block of circu its one of the three digital signature analysis DSA tests shou ld be used to troubleshoot individual circu its Waveforms are provided in table A9 7 to ...

Page 556: ...alyz ing a fixed sine signal and all the rest of the diagnostic tests for this board pass investigate the pseudorandom number generation block It is reset prior to doing the math for the special functions of this test so that the resultant checksum is repeatable If the PRN generator is not reset or does not operate correctly the checksum generated won t always agree with the stored checksum The FF...

Page 557: ...n RAM against a known number If the numbers are identical the FFT Interrupt test passes FFT RAM TEST This test is a self test run by the TMS320 FFT microprocessor on its own internal RAM The test program resides in ROM in the FFT microprocessor system The system CPU addresses the FFT board and loads a command to run the RAM test After the test is complete the FFT board interrupts the system CPU an...

Page 558: ...of the ROM integrated circuits The operation of the microprocessor is partially verified by this test because the address l ine outputs of the TMS320 are identical to the ROM input lines Test 2 may be used to test most of the circu its on the FFT board The only exceptions are the global bus interface circu its These require a special clock and are covered in test 3 Test 3 may be used to test the g...

Page 559: ...1 7 23 9635 22 1 734 21 8P54 U301 9 8551 only 1 0 91 CO data 1 1 3COC output 1 3 U6H7 lines 1 4 6P56 1 5 29C5 1 6 CFPC 1 7 A484 Return all jumpers to the normal N position either position OK for 1 2 Digital Signcllture Test 2 Table A9 3 FFT Signature Analyzer Setup 2 Signal Polarity Connection G round A7 J 5 1 Clock Neg edge A7 J 5 3 Stop Neg edge A7 J 5 4 Start Pos edge A7 J 5 5 Test 2 is activat...

Page 560: ...7H P GOBOUTL 14 1 3 I nternal data bus SOBUSOUTL 1 2 I O BO U503 1 8 31 H P LDHWCRL 1 1 IOB1 1 4 F8F2 LDCTR2L 10 I OB2 16 06FO LDPGSL 9 I OB3 1 7 001 P 7 I O B4 1 5 U7P8 R I RQSYSL U21 7 1 5 lOBS 1 1 5204 G O B I N L 14 I O B6 1 3 0746 PROM I N L 1 3 I O B7 1 2 1 1 80 SOBUSINL 1 2 I OB8 U403 1 8 9376 SA BUSINL 1 1 I OB9 1 7 P682 10 I O B1 0 1 6 349C CLRSCA LEL 9 I O B1 1 1 5 053U BFSU BADL 7 I OB1...

Page 561: ...7 FU43 SEQSELO 1 2 FFTWR 1 6 9758 POSTI NCL 1 5 1 5 FU I O B7 U405 2 REQG BL 1 2 31 76 I O B6 3 l O BS 4 LOCAL 1 1 3H40 I OB4 5 use test 3 for signatures of these signals I OB3 6 I OB2 7 Sequence decoder I O B1 8 1 0BO 9 SEQSEL1 U11 5 1 A1 07 S EQS ELO 2 OAC9 LDHWCRL 1 1 CTR20NL 3 8C22 CTR1 ENL 4 4POA LEV2 1 9 LEV1 1 8 POSTINCL 5 1 5FU LEVO 1 7 CLKOUTL 6 0000 TBSEL2 1 6 REQGBL 7 31 76 FFTWR 8 9758...

Page 562: ...Generator FA2 7 FA1 8 CLRPRNL U1 05 9 P1 H F FAO 9 GOBOUTL 1 2 OHPC 1 1 284A Global Oata Bus Interface PRN 14 5828 I OB1 5 U51 6 2 U51 5 1 9 U1 06 1 1 8H75 I OB1 4 3 1 8 5 21 U9 IOB1 3 4 1 7 U1 07 1 1 5H4P I OB1 2 5 1 6 U1 08 1 1 F61 F I OB1 1 6 1 5 U1 08 4 PC89 I O B10 7 14 U408 1 1 FA70 I O B9 8 1 3 IOB8 9 1 2 Test Bit Mux I O B7 U51 4 2 U51 3 1 9 0lVBY4 U206 2 1 384 IOB6 3 1 8 0 lVBY2 1 H4UC lO...

Page 563: ...6052 1 3 2 A7C1 1 2 1 A51 2 7 1 5 U9F5 6 U21 0 1 3 UU1 1 2 1 1 A1 72 3 10 5P63 I O B3 U409 9 9 OCA2 I O B2 10 7 9580 I O B1 1 6 C207 1 0 BO 1 5 5 859C LOCTR2L 1 1 4 6530 OEC2L 4 3 P490 I NC2L 5 2 A634 1 3 1 4048 1 2 1 5 60H1 7 6 U41 1 9 053U 2 10 349C 3 1 P682 1 5 9376 1 1 5P63 4 CPH4 5 PP8P 1 3 3044 1 2 9PAC 7 80UA 6 4673 2 3800 3 6HOA U41 0 9 1 1 80 10 0746 1 5204 SERVICE Signature U7P8 5P63 21 ...

Page 564: ...9580 LEV2 1 2 5 C207 TYPE2BF 1 5 1 1 859C Butterfly Subroutine Address ROM 14 6530 3 5603 SCALEO U502 1 0 6 U4C2 SCALE1 1 1 PASSOONE 1 2 10 662A TYPE2BF 1 3 1 3 83C6 4 86H2 BFSU BAOL 1 5 7 01 69 I D BO 1 I D B1 2 9 OCH4 I D B2 3 1 2 01 52 1 4POA I O B3 4 U309 2 P490 I O B4 5 l O BS 6 5 A634 I O B6 7 1 1 4048 14 60H1 IOB7 9 3 UAH2 6 9AC9 10 281 3 1 3 FH82 4 349A 7 6AH1 9 1 U59 1 2 4282 1 4POA AC B ...

Page 565: ... FA8 16 C904 FA1 0 6 FA1 0 1 2 6739 FA1 1 7 FA1 2 8 AC B1 U31 3 1 1 U59 FA1 3 9 AC B3 2 349A AC B5 3 OCH4 LDCAL 1 1 ACB7 4 86H2 1 9 1 8 AC B9 5 7FA4 1 7 FA1 1 9 7H94 FA3 1 8 85PP 16 FA5 1 7 F6C8 1 5 14 FA7 16 5C91 1 3 FA9 1 2 1 P6P U31 5 1 0 U31 7 1 0 AC BO U307 1 2 4282 9 9 PASSBITO 1 3 1 4AA 8 8 FAO 1 1 4282 7 7 ACB_ is address count bus 6 6 FA_ is FFT address bus 5 5 4 4 3 3 25 25 24 24 21 21 2...

Page 566: ... O B1 4 1 2 F091 I O B1 5 1 1 77H P Retu rn all jumpers to the normal N position either position OK for J1 3 Digital Signature Test 3 Connect the signatu re analyzer as described in table A9 5 Table A9 5 FFT Signature Analyzer Setup 3 Signal Polarity Connection Grou nd A7 J5 1 Clock Pos edge A7 TP3 Stop Neg edge A7 J 5 4 Start Pos edge A7 J 5 5 note change from test 2 Test 3 is activated by perfor...

Page 567: ...1 2 1 2 GA1 5L 1 8 1 8C1 FFTMG 1 3 GA1 4L 1 7 4UAU 1 1 GA1 3L 16 7FH4 FFTMR U21 1 1 2 1 3 GA1 2 L 1 5 U839 FFTWR U501 2 GA1 1 L 14 A440 REQGBL 3 GA1 0L 1 3 4020 LDG DBRL U21 4 3 GA9L 1 2 1 5 PP GRjGWL U21 1 8 GA8L U511 1 9 4PP9 MGFFTL U21 5 1 3 GAll 1 8 U5U7 GDSL U21 4 2 GA6L 1 7 4291 MRFFTL U21 1 1 1 GA5L 16 6F84 GA4L 1 5 3831 GA3L 14 A997 GA2L 1 3 FF53 GA1 L 1 2 P39F Return all jumpers to the no...

Page 568: ...ition and press the reset button on the CPU board A2 S1 SRT STP TST 1 1 4 Hz Time period and pu lse shape Signal at pin 4 and 5 of 5 SVdc _ r r r 0 r r 0 DSA connector Scale 1 V d iv Timebase 500 ms div OVdc b _ _ _ _ _ _ _ _ _ _ b Offset 2 5 V Delta V 5 V Trigger Ch 1 Coupling dc 2 Put 3 and J4 in the test position and 2 in the TST2 position SRT STP TST 2 1 2 kHz Time period and pu lse shape I Si...

Page 569: ...2A D After Repair Adjustments and Tests Table A9 iB After Repair Adjustments and Tests Perform th e following Section Diagnostic Tests Test All VI I Adj ustments None Performance Tests None SERVICE 8 1 1 9 8 1 20 ...

Page 570: ......

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