HP 3562A, Service Manual

Page: 494 / 570

S E RV I C E
MOD E L 3562A
8-44
A. Local Oscillator Diagnostics
When the LO FU NCTN key is pressed, the LO functional self-tests cause the phase
accu m u lator and the sine ROMs to output a value to the A2 System CPU. The system
CPU compares the value to a known good val ue. The tests are executed twice. The fi rst
execution of the tests substitutes c lock s ignals ( I nt Clock) generated in the LO assembly
for the external clock (Ext Clock) signals SYNC2 and 1 0.24 MHz. The second execution
of the self-tests uses the external clocks. Perform the LO functional test by pressing the
HP 3562A keys as fol lows:
SPC l
feTN
. . . . . . S E RVIC
T E ST . . . . . . T E ST
SOURCE LO
FUNCTN
Use the fol lowing descriptions to help isolate the fai l u re:
1 . LO I nterface Test
This test verifies the System Bus I nterface su bblock by read ing data to and from the
PIA (A4 U36). If 'LO I nterface Test FAI LS' is displayed, start troubleshooting with
components A4 U36, U32, U33, U37, and U24 in the System Bus I nterface Subblock.
LO Timeout 'messages'
An LO timeout message can be caused by one of several components fail ing in the
system bus interface, contro l , and timing circuits. However, the probable cause of
the fail u re is A4 U36, and U37 in the system bus interface or A4 U55, U56, U68, U46,
U51 , and U1 4 in the control and tim i ng c i rcu its.
2. I nternal and External C l ocks
The external clock test uses the 1 0.24 MHz c lock from the A31 Trigger and the SYI\lC2
from the A6 Digital Fi lter (norm a l operating clocks). The i nternal clock test su bstitutes
these c locks for clocks generated on the LO assembly. The i nternal c locks are
significantly slower than the external clock signals.
If the fai l u re message is 'LO Ext Clock Phase Values FAI LS', ' LO Ext Clock Output
Val ues FA I LS' and the other LO self-tests pass, the external c locks are fai l i ng. Start
troubleshooting with the SYNC2 and 1 0.24 MHz i nput circu its (A4 U75, U68). This fail u re
can also be caused by timing problems throughout the assembly since the external
signals are at a higher frequency than the i nternal signals.
If the failure message is 'LO I nt Clock Phase Values FAI LS', 'LO I nt Clock Output Values
Fai ls' and the other LO self-tests pass, the internal clocks are fai l i ng. If this occurs,
the possible fail i ng components are A4 U32 and U36 in the system bus interface, A4
U68, U72, U74, and U75 i n the control and timing circu its.
If the LO I nterface Test passes and both the external and internal c lock tests fail, the
problem is probably not in the system bus interface or the control and timing circu its.