HP 3562A, Service Manual

Page: 361 / 570

C I RC U I T D ESCRI PT IONS
MOD E L 3562A
6-1 46
U DSL
U PPER DATA STRO BE
Active Low
U N LOCK
V I O L
VMAL
WRITE L
Signal from the A2 System CPU indicating data is transferring on the
upper half of the system data bus (DB L to D1 5 L). When U D S L goes
low for a read cycle, the A2 System CPU is expecting val id data to
be placed on the upper half of the data bus. I n the write cycle, a low
on UDSL indicates there is val id data on the upper half of the data bus.
U N LOCK
When this signal from the A31 Trigger assem bly is active, the phase
lock loop is un locked. It is only active when an external reference is
used. U N LOCK is passed through the A1 Digital Source assem bly so
the A2 System CPU can read the signal.
VAL I D I/O ADDRESS
Active Low
An I/O assem bly m ay be add ressed only when this line is low. This
signal from the A2 System CPU is part of the address for the fol l owing
assem bl ies:
A1
A4
A6
A7
AB
A9
Digital Source
Local Osc i l l ator
D igital Filter Contro ller
Floating Point Transform Processor
G l obal RAM/D isplay
Fast Fourier Processor
VIOL is also used by devices in the A2 System CPU assembly.
VAL I D MEMORY ADDRESS
Active Low
Signal from the A2 System CPU to the A4 Local Oscillator indi cating
the beginning of a synchronous bus transfer. After receivi ng the val id
peripheral address signal (VPAL) from the local osc i l lator, it asserts
VMAL synchron ized with the enable c 1ock (H,j B LL).
Active Low
Handshake signal from the A4 Local Osc il lator to the A2 System C P U .
The local osc illator sends the VPAL signal to the system CPU when
the LO recogn izes that it has been add ressed . When the system CPU
receives the VPAL signal, it asserts the valid memory add ress signal
(VMAL) which is synchron ized with the enable clock ( E N B L L).
READ/WRITE
This signal defines the system data bus transfer as a read or write cycle.
When W R I T E L is high the A2 System CPU is reading data from the
system data bus. When W R I T E L is low the A2 System CPU is writing
data onto the system data bus.