HP 3562A, Service Manual

Page: 283 / 570

C I RC U I T DESC R I PTIONS MO D E L 3562A
Internal Signal Descriptions
6-62
CCA
CCB
CCC
CCE N
CCODE
C LK I N H IY
CLKIN LOWY
C LRIRQ
C P D L
E A
E N H IYO UTL
EXPL
10 to 13
LD H IY
COND I T ION COD I N G
Output l i nes of the test and j u m p PROM which controls the
in put selection of the cond ition code m u ltip lexor.
CON DI T I O N CODE E NABLE
E nables the condition code m u ltiplexor.
CON D I T I ON COD E
When the sequencer receives CCODE, it branches out of the wait loop
and starts the FPP process.
C LOCK IN H IG H Y BUS
S ignal from control PAL 2 which clocks the global data bus into the
Y8 to Y23 global bus registers.
C LOCK I N LOWE R Y BUS
Signal from control PAL 2 which c locks the global data bus into the
YO to Y7 and B1 7 to B23 global bus registers.
C L EAR I NTE RRU PT REQU EST
Clears the I nterru pt Request (I RQT3 L).
CONSTANT P I PE L I N E DATA
Output signal of the B bus, Y bus control register which enables the
pipeline data bus onto the Y bus.
E NA B L E A
This signal from the bus contro l PROM selects the i nput to the ALUs
(ALUs internal RAM or Y bus).
E NABLE H I GH Y BUS OUT
Signa! from control Pl\.L 2 vvhich enables the global bus iegisters output
from Y8 to Y23 onto the global data bus.
registers o utput
from YO to Y7 and B1 6 to B23 onto the. global data bus.
EXPON E NT
This signal enables the gl obal bus registers output onto the 81 7 to B23
bus l i nes.
SEQU E NC E R I NSTRUCT ION
In test mode, these li nes become the sequencer's i nstruction .
LOAD H IG H Y B U S
Signal from contro l PAL 2 which latches the YB to Y23 i nto the g lobal
bus reg isters.