HP 3562A, Service Manual

Page: 289 / 570

MOD E L 3562A C I RC U I T D E SCRI PT I O N S
D I SPLAY DMA WO RD/ADDRESS COUNTERS (A8)
The system CPU puts the beginn ing add ress and the length of each buffer on the system
d ata bus. They are clocked i nto the d isplay DMA word (U400, U401 , U500) and address
(U600, U601 , U602, U603) counters by the ALOADL and WLOADL signals from the disp lay
control ler. E ach time a display memory grant is asserted, the add ress from the add ress
cou nters flows through the d isplay add ress drivers (U604, U605) to the memory add ress
m u ltiplexer. After the display data has been transferred to the display i nterface board
(A1 7), the cou nt enable line (COUNT E N L) is asserted low. The address cou nters increment
and the word cou nters decrement by one. This process conti nues u ntil the entire buffer
has been transm itted to the display interface. The word cou nters have gone to zero,
asserting the TC L (terminate cou nt) l i ne low. This signal generates an interrupt to inform
the system CPU that the buffer transm ission is comp lete.
D I S PLAY RE FRESH TIMER (A8)
The display m ust be refreshed at a rate of 60 H z or greater. U1 01 d ivides down the 8 M H z
clock to 61 H z . U201 is clocked by th is 61 Hz signal and puts out a SYNC pulse every
1 6.4 msec. E ach time the system C P U starts a new d isplay frame it sets D1 5 on the system
bus. This signal is used to reset the d isplay refresh timer to coord inate the sync pu lses
with the new frame information.
D I SPLAY I NTE RFAC E (A1 7)
One section of the display interface board buffers information and control signals from
the global bus to the 1 345A d isp lay. This circu itry consists of two i nverting registers
(U1 , U2) for the data I ines and a non-inverting bus driver (U3) for the control l i nes.
The other section of the interface board is the output protection circu itry between the
d isplay X, Y, and Z outputs and the i r respective rear panel connectors.
Internal Signal Descriptions
AtOADt
Address load, active low. Al lows the contents of the system address
bus to be loaded into the d isplay add ress cou nter.
. ..
m <"' �. ,,�V_"._, U �
__ ���J� --��
of frame with negative to positive assertion of t
�
e
B RST l
B U S EN1
B U S E N 2
CO
through
C7
SYNC signal.
Board reset, active low. Software reset for the global RAM board,
originates from the system C P U .
T i m i ng signals w h i c h enable the global b u s to perform a transaction.
Cou nter add ress bus l ines 0 through 7.
6-69