HP 3562A, Service Manual

Page: 339 / 570

C I RC U I T D E SC R I PT I ONS MOD E L 3S62A
6-1 24
Table 6-A33 Control Word
le
Pin No. Description
Function
If bit
=
"1 " If bit
=
"0"
7
ac/dc Coupling
d c a c
8
I nput E nable D isconnected
Connected if Sou rce
E nable is low
9 I nternal Disables inputs I nputs can be
Sou rce E nable and connects connected
i nternal source
1 0 G round Low Return signal shorted
to chassis grou nd
Note
1 1 Attenuation
o
dB Only one should
1 2 Select
20 d B b e selected at a
1 3 40 d B time.
For attenuator settings refer to tabl e 6-A32a.
Attenuators and Buffers
The input re lay switches perform the fol lowing fu nctions: isolate the input connectors
when the internal sou rce is connected, provide ac/dc cou p l i ng, and select 0 dB, 20 d B,
o r 40 d B input attenuation. The attenu ated signal leads to a FET source-fo l lower buffer
and then a u n ity gai n operational ampl ifier (U351 ) with the FET in its feedback loop. As
a
resu lt, any offsets in the sou rce fo l l ower are e l i m inated.
The bootstrapping of the power suppl ies consists of two cu rrent sou rces, one positive and
one negative, with two em itter followers. The em itter fol lower provides the power to the
.
b
uffer while the cu rrent source keeps the voltage across the zener at S.6Y above the input.
T h is creates a stable power su pply for the buffer so it has un ity gain for a wide voltage
range even at high frequencies. The 30V protection diodes are also bootstrapped to the
power supply to avoid distortion. The LOW side of the input has the same configu ration.
The input overload detector circuit receives its input from the H IG H signal path. It is active
w hen the input signal to ground is over the l i m it of 20Y with no attenuation. Resistors
RS03 and RS02 attenuate the signal for the com parators (US01 A, US01 B). The atten u ated
s ignal is compared to a positive and negative reference voltage. If the value is greater
than the reference level, the input overload signal (COYLD) is sent to the overload c ircu it
on the ADC assemb ly.
.
Common Mode Rejection DAC
The common mode rejection DAC is a d iscrete DAC com posed of operational ampl ifiers,
FETs, and a res istor network. The DAC receives its digital input from the interface shift
registers. The common mode rejection DAC's output is an effective resistance val ue which
c o m pensates for d ifferences between the H I G H input and the LOW input circu its.