HP 3562A, Service Manual

Page: 512 / 570

SERV I C E
MO D E L 3562A
8-62
B. Signal Verification
Verify the fol lowing signals and supply voltages:
1 . Check the + 5V level at A S TP5 and the + 8V level at AS U1 01 -7 and AS U1
'I
4-7.
2. The phase clocks for channel 1 and channel 2 and their test locations are:
CH1 4>1 AS TP1
CH1 4>2 AS TP2
CH24>1 AS TP3
CH24>2 AS TP4
Com pare the phase cl ocks as fol lows:
a. The two clocks for each channel should vary between 0 and + 8V and shou ld
be 90° out of phase. See waveform #1 , tab le A5-1 .
b. Phase clock CH1 4>1 should be in phase with CH24>1 . See waveform #2, table 1\5-1 .
c . Phase clock CH1 4>2 shou ld be in phase with CH24>2.
3. Verify the signals CH1 S H I FT1 (AS U401 -1 9) and CH2SH I FT1 (AS U41 5-1 9). (See
waveform #3, table A5-1 ). If each of these signals is a 200 ns p u l se at a 256 kHz
rate, then the channel 1 and channel 2 d igital filters are accepting data. If the
digital fi lters are not accepti ng data, the pu lses occur at a 51 2 kHz rate.
4. Verify the SYNC2 signal at AS U401 -20 and AS U41 5-20 (waveform #4, table A5-1 ).
The SYNC2 signals are only active when the digital fi lter has accepted a data point.
5. Verify the fol lowing bus requests from the fi lter controls (see waveform #5, table
A5-1 ):
CH1 BR2 AS U401 -47
CH1 BR3 AS U401 -34
CH2 BR2 AS U41 5-47
CH2 BR3 AS U41 5-34
If these signals are correct, the filters are asking for the bus.
6. Verify that the MCLK signal (AS TP20) is changing between TTL levels. This indicates
that channel 1 and channel 2 d igital fi lter circu its are being synchronized.
7. Verify that signal CH1 1 0 E N is correct (waveform #6, table A5-1 ). Verify that signal
C H 2 1 0 E N is a s i m i lar but non-periodic pulse.
8. Verify that signal IRQT5L (A6 U401-6) is changing between TTL levels. This indic.ates
that the i nterrupt circu its are passing data.