S E RV I C E
MO D E L 3562A
8-1 4
4. To verify the device decoder PAL and buffer, use a logic probe to check the fol lowing
signals are the correct TTL level:
U303 pin
1 2 Toggling
U401
1 3 Toggling
1 4 Toggl ing
1 5 Toggling
1 6 Toggling
1 7 H igh
1 8 Toggling
1 9 Togg l i ng
5. Press the H P 3562A keys as fol lows:
RETURN . . . . . . LOOP
OFF
LOOP
ON
p i n
2
7
1 0
1 1
T E S T
S O U R C E
Toggling
Toggling
Toggl ing
Toggling
FR E N D
I NTFCE
6. Use a logic probe to verify the fol lowing signals are the correct TTL level:
U303 pin
1 2 H igh
1 3 Toggling
1 4 H igh
1 5 H igh
1 6 Toggling
1 7 Toggling
1 8 Toggling
1 9 Toggl ing
7. Use a logic to verify the DS data l i nes are togging (FR END I NTFCE in loop mode).
Some of the li nes w i l l toggle slowly. Use the fol lowing test locations:
U406 pins 1 and 11 through 1 9
U405 pins 1 1 through 1 8
8. Press A2 S1 . After the power-u p tests are complete, verify the fol lowing signals are
the correct TTL level:
Test location
U203-2
U304-6
U304-9
U302-4
Signal Name
T E ST
N RSTL
BRST
R E S E T L
TT l level
Low
H igh
H igh
H igh
9. If the fault has not been found, go to part E.
Summary of Contents for 3562A
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Page 16: ...GEN ERAL INFORMATION MODEL 3562 T bJe 1 3 Specifications cont 1 10 ...
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Page 207: ...MODEL 3562A CR Cl ...
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Page 213: ...r A1 a pQWERSuP PLY I 03562 66518 REV A REV 8 8MPOUT 58 58 FRONT REAR P ANEL ii O N ...
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Page 237: ...Sample Clock SAMP DS DATA oe _ _ _ _ _ BUS NOTE FULL SPA BASi BAI MODE ...
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Page 259: ...WRITEL A22L l cc E Vl 8 MHz A23L ASL Inverting A1L A21 L D rivers r ...
Page 305: ...c c I O Sequencer S r J Sequence Decoder ...
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Page 324: ...EXT TRIGGER TRIG 1 TRIG 2 CALTRIG CNTLD COMI W CNTCLK LDTRGL RESETL ...
Page 327: ... RH r I N EXT BUFFER SAMPLE _ _ _ IN ...
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