HP 3562A, Service Manual

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MOD E L 3562A
C I RC U I T D E S C R I PTI O N S
6-5 A3, ROM
The A3 ROM board functions as an extension of read only memory for the system CPU
board. The ROM board stores most programs for the H P 3562A except i n itial start-up
routines. A l l com m u n i cations between the system CPU board and the ROM board occu r
over the system bus. Refer to the tim i ng diagram (figure 6-A3a), block diagram (figure 6-A3b),
and the schematic (figure 9-A3) as referenced in the fol lowing circuit descriptions.
The fol lowing descri ptions apply to the cu rrent ROM board. This board al lows flexibil ity
in the n u mber and type of ROM chips used. ROM density (size) is selected by pl acement
of jumpers in the OEL l i ne to the ROM chips, the add ress comparator section, the delay
section, and the ROM decoder section.
Address Comparator
The address comparator verifies that the ROM board is add ressed and asserts the ROM
select (ROMSE LL) l ine low. The ROMS E LL signal does the fol lowing�
1 . Returns DT ACKL to the system CPU to acknowledge that the ROM board was addressed.
2 . E n ables the ROM Decoder.
3. E n ables the Data Bus Driver.
ROM Decoder
The ROM decoders (U21 , U22, and U23) are 1 -of-8 decoders. They generate the chip enable
(CE1 L through CE20L) signals by decod ing system add ress l ines A1 6 through A21 . The chip
enable signal cau ses the selected ROM pair to put data on the data bus.
Delay
U1 3 and U1 4 are used to delay the DTACK L signal based on the speed of the s l owest
component on the ROM board. The piacement of RSO determines the length of the delay
(from 0 to 4 clock cycles).
The memory section of the A3 ROM board consists of 32k by 8 bit read-only-memory chips.
The chips are addressed by system add ress l i nes A1 through A1 6 and enabled by C E1 L
th rough C E20L. The i nverting drivers pass the system address l ines from the system bus
to all ROMs. The mem ory is arranged as a lower byte (DO through
07,
stored i n U1 01
through U1 20) and an upper byte (D8 through D1 5; stored in U201 through U220). E ach
CE line enables a lower byte chip and an upper byte chip to put all sixteen data bits on
the bus simu ltaneously.
Data Bus Driver
When enabled by the ROMSE LL signal, the data bus drivers transfer data from the ROM
data bus to the system data bus.
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