HP 3562A, Service Manual

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MODE L 3562A
C I RC U I T DESC R I PT I O N S
COUNTERS ONE A N D TWO
Address generation begins with two cou nters. Counter One (U209
&
U21 0) is an up-cou nter.
Cou nter Two (U409-U41 1 ) is a l oadable, cou nt-up or count-down counter on the i nternal
data bus. Cou nter Two appears as a write-only port to the TMS320 system . Typ ical ly, one
cou nter is used to keep track of input add resses while the other is used to' keep track
of output addresses. The output of one of the two counters is selected by the counter
m u ltiplexer (U309-U31 1 ) to drive the add ress count bus.
ADDRESS TRANS LATOR
The address translator (U31 3 & U31 4) consists of 2 PA L I Cs used to convert addresses on
the address count bus to addresses on the FFT address bus depending on the FFT l evel
and whether a read or a write operation is required. Several bits from the hardware control
register are used to determ ine how the data on the address cou nt bus is changed to FFT
address bus data. PASSBITO is a control line (see schematic) used to mask off the least
significant bit of the add ress during a com plex transform requ iring access to only even
(real) window coefficient add resses.
PAG E REG ISTER
The upper bits of the FFT add ress bus come from the Page Register (U31 2). This register
on the i nternal data bus is a read-on ly register activated by the port decoder. I t selects
the RAM location for input and output blocks. The TMS320 sets the inputs which are written
to (once) at the beginning of the transform . The page register specifies the four most signifi­
cant bits of the FFT add ress bus dependent on whether the memory access is a read or
a write (state of the FFTWR signal) and whether the i nformation being accessed is wi ndow
data or FFT data (state of the W I ND PG L signal). (User defined windows are stored in RAM.)
CO E FF I C I ENT ROM
The coefficient ROM (U31 5 and U31 7) appears on the internal data bus as a read-only
register activated by the port decoder. The FFT add ress bus drives the ROM i nputs. The
pU ipose of this circuit is to convert FFT address i nformation into coefficients used by
the TMS320 system for the transform process.
There are two busses connected to the FFT board; the system bus and the global bus.
E ach is composed of address l ines and data l i nes. The system bus allows com m u n ication
,between the system CPU and the TMS320 system. The global bus allows the TMS320 system
access to the global RAM which holds user defined window information and data for the
Fourier transformation. The FFT board hand les a l l memory access di rectly by req uesting
mem ory and contro l l ing the global bus. The interface hardware consists of the fo l lowing
blocks:
System bus i nterface: G lobal bus interface:
•
System address bus buffer
•
G lobal address bus interface
•
System data bus i nterface
•
G lobal data bus interface
•
FFT interrupt circu it
•
G lobal bus handshaking c i rc u it
•
CPU interru pt circ u it
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