HP 3562A, Service Manual

Page: 350 / 570

MO D E L 3562A
C I RC U I T D E S CR I PT I O N S
DSH I FTEN
DTACKl
EOC
EOI
E N B ll
DATA SH I FT
Sh ift clock from the A1 Digital Sou rce to the A30 Analog Sou rce that
is used to shift in the DACDA T data.
DATA TRANSFE R ACKNOW L E D G E
Active Low
This is an open collector signal that is pu l led up to
+
5V on the -A2
System CPU. After an assembly receives the data strobes (UDSL, LDSL,
or ASL) and has performed the appropriate read or write operation,
it sends the A2 System CPU the handshake signal DTACKL. This signal
indicates that the data has been transferred. The CPU puts the bus
cycle in the wait mode unti l it receives the DTAC KL signal or 1 ms
has passed and B E RRL is asserted. The fol lowing assembl ies use the
asynchronous DT ACK L signal for d ata transfer:
A1
A3
A6
A7
AB
A9
A1 5
D igital Sou rce
Program RoM
D igital Fi lter Controller
Floating Point Transform Processor
G lobal RAM/D isplay
Fast Fourier Processor
Keyboard
E N D OF CONVE RS ION
(A32, A34 TP605)
This signal is used by the A32 ADC 1 and the A34 ADC 2. When both
assem bl ies are installed, ADC 2 tel l s ADC 1 when it is done with a
conversion.
E N D
Signal to and from the A 2 System CPU to the A22 H P-I nterface Bus.
This 'line is used to indicate the end of a multiple-byte message on
the bus. I t is also used in paral lel pol l ing.
E NABLE
Active Low
EXT SAM P LE I N
EXTE RNAL SAM P L E I N PUT
(A31 J 501 )
Sample rate from the rear panel to the A31 Trigger assembly. This signal
is active only in external sam ple mode.
EXT TRIGGER
EXTERNAL TR I G G E R
(A31 J2)
The external trigger input from the front panel to the A31 Trigger
assembly. This input has a 50 kO input resistance and a range of ± 1 0V.
6-1 3 5