HP 3562A, Service Manual

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MO D E L 3562A
R D I B C I N T L
RDIBCSTAT l
SETB lKREADYl
SFlTRST
STOPE N l
T P U lSE
TRIGATE l
T R I G G E RED
T R I G G E R F lG
WRI BCCM D l
WRINTMSKl
C I RC U I T D ESCR I PT I O N S
Read input buffer contro l interrupts
Read input buffer control status. Latches status word from
status reg ister onto the local data bus
Term inates a measurement by generating a CPU interrupt
Set fi lter reset
Stop enable
Test pulse, replaces system clock signal when A6J 2 is i n test
position
Signal from trigger control ler to cou nters to continue counting
input sam ples
See FREE RUN
Set if a valid trigger event has occu rred afte r being armed
Write input buffer control command. Clocks commands from
the local data bus into the command register
Write interrupt mask. Used to mask interrupt fl ags
Internal Signal Descriptions, AS
2XC lK l
CH1A[DDATA
CH1AEN, CH2AEN
CH1 B R1 , C H 2 B R1
CH1 B R 2, C H 2 B R 2
CH1 B R3, C H 2 B R3
CH1 DACK3 l,
CH 2DACK3 l
CH1 DIS1, CH2D IS1
CH1 DI S2, CH2 DIS2
CH1 D IS3, C H 2DIS2
CH1 DMACS,
CH 2DMACS
The buffered on-board 1 0.24 MHz clock
Serial data inputs from the ADC assembly which have
CH2AjD DATA been reclocked by U51 2
Channel 1 and channel 2 add ress enable
Bus requ ests for DMA channels 1, 2, and 3
Data ack nowledge, channel 1 and channel 2
Disable DMA modes 1 , 2, and 3
E nable channel 1 or channel 2 of the DMA Poi nter Register
and DMA Controller
6-55