HP 3562A, Service Manual

Page: 288 / 570

C I RC U IT D E SCRI PTIONS
MOD E L 3562A
6-68
Dynamic Memory Array
The RAM itse lf is a 64k by 1 6 bit dynamic memory array constructed from 1 6 64k by
1 b it dynamic RAM chips. The 1 6-pi n RAM chips have 8 address i nput l ines and requ i re
add ress mu ltip lexing to receive 1 6 add ress bits.
Address Multiplexer and Address Drivers
The add ress mu ltiplexer (U61 1 and U 61 2) mu ltiplexes the 1 6 gfobal add ress li nes and
transfers the address 8 bits at a time to memory through the memory address drivers (U1 1 1
a n d U21 1 ).
Memory Control Drivers
The memory control circuit generates the row add ress strobe (RAS L L and RAS U L) and
column address strobe (CASLL and CAS U L) signals. These are clock signals which strobe
the mu ltiplexed add ress into the RAM .
Memory Refresh Timer and Refresh Address Counter
The dynamic global memory must be refreshed to pre�ent loss of data. Every 8.5
JlS
the
memory refresh timer (U404) sends a memory refresh request (M RRFSH L) to the arbiter.
When the arb iter issues a memory refresh grant (MG RFSH L), the output of the add ress
mu ltiplexer is disabled. The refresh add ress cou nter (U51 1 and U51 2) is enabled. The output
is appl ied to the memory add ress drivers to set up the memory row to be refreshed. The
row add ress strobe signals (RAS U L and RASLL) are enabled and a read memory operation
refreshes the RAM memory row.
Global Bus Transceivers
The global bus transceivers (U609 and U61 0) are bi-d i rectional, inverti ng buffers which
transfer data betwee n the global data bus and memory locations. The RAMG R/GWL signal
determ i nes the d i rection of flow (if h igh, the transaction is a read cyc le; if low, it is a
write cyc ie).
The display is presented to the viewer in the form of a frame. A frame consists of from
3 to 20 buffers (e.g. data, grid, scales). Each of these buffers has a predefined s ize and
location in global memory. The display contro l/interface section mon itors and d i rects the
flow of this data to the 1 345A display in response to control commands from the A2 System
CPU.
D I S PLAY CONTRO L L E R (A8)
The display controller (U303) is a field programmable logic seq uencer or state machine.
Among the i nputs to the disp lay contro l ler are address and control l i nes from the system
b u s . The synchronizing register (U302) synchronizes the control i nputs with the 8 M H z
c lock from the system CPU.