HP 3562A, Service Manual

Page: 277 / 570

C I RC U I T D ESCR I PTIONS, MOD E L 3562A
6-56
CH1 DMAL, CH2DMAL
C H 1 D REQ3, CH2D REQ3
CH1 EOPL,CH 2EOP L
CH1 HACK, CH2HACK
CH1 H REQ, CH2H REQ
CH1 H LFSCA LE,
C H 2H LFSCALE
C H 1 10 R L, CH210 R L
C H 1 10WL, CH 210W L
C H 1 1S1 L, CH 21S1 L
CH1 L01
CH1 L02
Channel 1 and Channel 2 di rect memory access
Data req uest, chan nel 1 and channel 2
Timing signal from DMA contro l ler to filter control block
Timing signals between DMA control lers and gl obal bus
DMA control ler
Status signal from the ADC assembly asserted wheneve r the
analog input exceeds half-range in ampl itude
Read/write signals in global bus DMA control block
Strobe from Global Bus DMA Contro l to Fi lter Control ler for
po l l ing status word
Signals from the Dig ital Filter Control ler assembly used to
used to sel ect the i nput to the d igital fi lters, The i nput can be
either the si ne/cosine data from the local oscillator or a locally
generated constant
C H 1 M E M R L, CH2MEM R L
C lock data through global data bus interface
CH1 MEMWL, CH2MEMWL
CH1 0VLD, CH20VLD
Status l ines to Fi lter Controller to indicate overl oad
CH1 + OVLD L, CH2 + OVLD L
condition on ADC assembly
CH1 - OVlD, CH2 - OVlD
CH1 RDFL TST ATL,
CH2 RD F L TST AT L
r�1C;;:I-III:'T1
_ . . . .., .... . .
CH1XCVREN ,
CH2XCVREN
CH1 *PH I*1
CH1 *PH I*2
CH1 <t>1 F B L
C H 1 <t>2FB L
D I R1 , D I R2
D MADTACKL
Read fi lter status channel 1 and channel 2
Signal fiO m the channel 1 filter control to request data from
the ADC assembi ies
an Input
Channel 1 and Channel 2 transceiver enable
5,1 2 MHz non-overlapping clocks
5' ,1 2 MHz clock signals
Control direction of data flow through global data bus interface
DMA data acknowledge