Digital Event/Timer/Counter
The Digital Event/Timer/Counter input connector is located on the mainframe. For exact layout and pinning see mainframe data sheet.
Digital input events
16 per card
Levels
TTL input level, user programmable invert level
Inputs
1 pin per input, some pins are shared with Timer/Counter inputs
Overvoltage protection
±
30 V DC continuously
Minimum pulse width
100 ns
Maximum frequency
5 MHz
Digital output events
2 per card
Levels
TTL output levels, short circuit protected
Output event 1
User selectable: Trigger, Alarm, set High or Low
Output event 2
User selectable: Recording active, set High or Low
Digital output event user selections
Trigger
1 high pulse per trigger (on every channel trigger of this card only)
12.8 µs minimum pulse width
200 µs
±
1 µs
±
1 sample period pulse delay
Alarm
High when alarm condition is activated, low when not activated (alarm conditions of this
card only)
200 µs
±
1 µs
±
1 sample period alarm event delay
Recording active
High when recording, low when in idle or pause mode
Recording active output delay of 450 ns
Set High or Low
Output set High or Low; can be controlled by Custom Software Interface (CSI) extensions;
delay depends on specific software implementation
Timer/Counter
2 per card; only available in 32 bit storage mode
Levels
TTL input levels
Inputs
All pins are shared with digital event inputs
Timer/Counter modes
Uni
-
and bi
-
directional count
Bi
-
directional quadrature count
Uni
-
and bi
-
directional frequency/RPM measurement
GEN3i
I3763-3.1 en HBM: public
583
