
Isolation
100V DC,
55
50V DC,
33
-
+
ADC
Isolated channel
50V DC,
33
70V DC,
33
-
+
ADC
Isolated channel
Chassis
V RMS
V RMS
V RMS
V RMS
Figure A.28:
Isolation schematic
Channel to chassis (earth)
33 V RMS,
±
50 V DC
Channel to channel
(Isolated GND to isolated GND)
33 V RMS,
±
70 V DC
Input signal to input signal
55 V RMS,
±
100 V DC
Analog to Digital Conversion
Sample rate per channel
0.1 S/s to 200 kS/s
ADC resolution; one ADC per channel
16 bit
ADC Type
Successive Approximation Register (SAR); TI ADS8401IB
Time base accuracy
Defined by mainframe:
±
3.5 ppm
(1)
; aging after 10 years
±
10 ppm
Binary sample rate
Supported; when calculating FFTs results in rounded/integer BIN sizes
Maximum binary sample rate
204.8 kS/s
External time base sample rate
0 S/s to 100 kS/s
External time base level
TTL
External time base minimum pulse width
200 ns
(1)
Mainframes using Interface/Controller modules shipped before 2012:
±
30 ppm
GEN3i
I3763-3.1 en HBM: public
405